Release Asterisk v2 (for miniCS) and updates compatible with SaftLib ( OUTDATED ) Asterisk is compatible to the control system releases R3, R4, R5 and R6 The rele...
Exploder5a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Note: Software/Version ...
Step by step guide to commissioning a new pexaria5: 1 Place powered off pexaria5 on ESD desk , ESD dischare! 1 Attach wrex2a addon board to baseboard WR1 (W...
Vetar2a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Needed components for each...
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
Snapshot "January 2016" The intention of this snapshot is twofold. First, to make improvement of White Rabbit available at GSI. Second, to provide again a consist...
Introduction to the General Machine Timing System The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. An important cons...
Main.MichaelReese 15 Feb 2018 PCIe WB bridge direct access mode PCIe timing hardware where the PCIe bridge has been modified to support the "direct access mode" ...
Main.MichaelReese 14 Aug 2023 Device Driver Tutorial EB slave WB master over PCIe The goal is to write an Etherbone slave that controls a wishbone master on the ...
PEXP Testing and Commissioning Guide Attention: This guide does not check the whole PCIe standard! Attention: This is NOT for FAT Required component...
Testing and Commissioning Guide for Pexaria5 Required components * Pexaria5 under test (named as P5UT in this guide) * PC with Intel Quartus (version 18...
Policies in the Timing Network * The timing network is managed by TOS and TOS defines the policies. * The timing network is a "field bus" synchronizing the...
Authentication of network nodes and assginment of virtual LAN using the White Rabbit switches 1. Introduction The 802.1x authentication standard is supported by ...
Releases and Snapshots of the Timing System Release A Timing Firmware Release packs together new features and requirements defined in our Development Road Map, ...
WR Switch: How To Cross Compile DIM THIS HOWTO IS DEPRECATED This describes the first try to cross compile DIM for a White Rabbit switch. DIM is a communication...
WR Switch: How To Flash a WR Switch THIS HOWTO IS DEPRECATED Introduction Most importantly, you should the WRS manual. For version 4.2, see here. Basically, al...
WR Switch: How To Cross Compile Hello World THIS HOWTO IS DEPRECATED This describes how I cross compiled hello world for switch Getting the Tools This assumes ...
WR Switch: How To Use a WR Switch THIS HOWTO IS DEPRECATED This is just a short list of things I found useful Login to a Switch * ssh via the management po...
WR Switch: Basic Remote Monitoring (Deprecated) THIS HOWTO IS DEPRECATED This describes how basic remote monitoring of White Rabbit switches can be done by usin...
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
UNILAC Chopper Firmware and Monitoring Introduction The main documentation about the (new) UNILAC chopper can be found here. This wiki page only describes som...
Main.MichaelReese 22 Aug 2017 Vetar2a: VME WB bridge direct access mode The normal mode of operation (after reset) of the Vetar2a card uses a VME wishbone bridge...
White Rabbit Switch Hardware 4.0 Overview This page summarizes the GSI requirements in context with the development of a new version of the White Rabbit Switch. ...
White Rabbbit UNILAC PZ (wr unipz) Introduction UNIPZ Figure: Most simplified view on UNIPZ (upper part). It is a combination of a Super UNIPZ and seven UNI...
WR MIL Gateway Introduction The White Rabbit to MIL gateway can work in one GID only. Its main features are. * listen to so called legacy event numbers, EvtNo...
HOW TO: Use xdot to analyze schedules Based on Graphviz dot language there is the tool xdot. A GSI fork of xdot (one of 136 forks) enhances this to analyze schedu...
WR Simulation How To This How To guide you in the simulation of the WR Core and WR Switch. Setup the Simulation environment You need a ModelSim runnig in your sy...
General Machine Timing System at GSI and FAIR The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. This is achieved by t...
How To: WR LLDP This how to describes how to use LLDP in WR Devices. It is not meant to clarify what is LLDP. Info (November 2017): The development is already in...