Exploder5a Commissioning Guide

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Note: This test is functional. It is not intended to cover verification & validation tests of the design!

Note: Software/Version of bel_projects used in this tutorial: fbe6e696e3c5c6c2402b6b86a169b2c63939e4fe @ proposed_master

Note: JTAG Settings for PROMO5 ->

• CPLD: SEL1=2, SEL2=8
• FPGA: SEL1=1, SEL2=4

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Needed components for each Exploder5a device

• SFP (green/purple)
• LC cable and a white rabbit switch
• USB cable (micro)
• WREX2a board (​THIS SHOULD BE A WREX2a BOARD!) Important: Add Sticker to the case (200MHz plug), if the device has no WREX2a)
• Power supply (if you don't use the PCIe cable with power delivery)
• Xilinx programmer (Platform Cable USB II, DLC10)
• Altera usb blaster
• OLE display module (UG-2864ASYDT03)
• Speaker + housing
• Addon board (DB2)
• LEMO cable(s) + 2 pin cable(s) (need for LVDSo/i 10 pin boxed header)
• PCIe cable (male to male, there are two kinds of cables: red/green = with power delivery, red/blau = without power delivery)
• Null modem cable
• 3,5mm audio cable (optional)

Important Steps

Programming the CPLD

Remark: Inspect the top-most (green) LED next to CPLD. If it is on, then it is more likely that CPLD is already programmed. In this case you can jump to a next section, unless you are not sure.

1. Check out bel_projects (git commit https://github.com/GSI-CS-CO/bel_projects.git --recursive; git checkout proposed_master)
2. Turn on power
3. Use Xilinx Platform Cable USB II and the promo5 adapter. Set the promo5 to SEL1=2, SEL2=8 and connect to the JTAG1 port
4. Run ISE
5. Load project bel_projects/syn/gsi_exploder5/cpld/exploder5_prog.xise
6. Process Menu => Implement Top Module
7. Tools Menu => Impact
8. Double-click Boundary Scan
9. Control-I => exploder5_prog.jed
10. Operations Menu => Program
11. Turn power off

Programming the FPGA

1. Attach the WREX2a board
2. Use Altera USB Blaster and the promo11 adapter (JTAG2USB). If the promo5 adapter is used, then set it to SEL1=1, SEL2=4
3. Turn power on
4. Open Quartus and program the FPGA (or use the command line: quartus_pgm -c 1 -m jtag -o 'p;exploder5_csco_tr.sof')
5. (optional) In case of an error "Error (213019): Can't scan JTAG chain. Error code 87." try again by unplugging and re-plugging Altera USB Blaster
6. (optional) Write this bit-stream into the SPI flash: eb-flash dev/ttyUSBx exploder5_csco_tr.rpd (in case USB is already programmed)
7. Once FPGA is programmed, connect an USB cable to the USBCON1 port and verify that the on-board USB controller is available: lsusb | grep -e "EZ-USB" -e "OpenMoko"

Programming the USB Chip

1. Run 'make' in bel_projects/ip_cores/etherbone-core/hdl/eb_usb_core
2. Make sure, that no other timing receiver is attached by USB
3. Erase the USB controller (as root): ./flash-fx2lp.sh -E
4. Program the USB controller (as root): ./flash-fx2lp.sh
5. Turn power off and on

Configuring (and programming) the SPI Flash Chip

1. Program the FPGA again: quartus_pgm -c 1 -m jtag -o 'p;exploder5_csco_tr.sof'
2. Verify again that the USB controller is available
3. Configure the SPI flash chip: eb-config-nv dev/ttyUSBx 10 4
4. Write the bit-stream into the SPI flash: eb-flash dev/ttyUSBx exploder5_csco_tr.rpd (in case FPGA is not programmed)
5. In case of trouble refer to TimingSystemHowFlashFTRNUser

Formatting the WR EEPROM (MAC address is stored here)

1. Go to bel_projects/ip_cores/wrpc-sw/tools
2. Run "make"
3. ./eb-w1-write dev/ttyUSBx -i 1 0 320 < sdb-wrpc.bin

Check White Rabbit

1. eb-console dev/ttyUSBx
2. Type in "gui", white rabbit status should be: locked and calibrated

   Synchronization status should be: + Servo state: TRACK_PHASE + Phase tracking: ON You should also see 4 leds at the front panel: + red = traffic/no-link + blue = link + green = timing valid + white = PPS

3. Press ESC to quit
4. Type in "mode master", node should be able to lock the PLL and become a master
   Quit console
5. Turn power off and on

Check EEPROM and set MAC

1. Run eb-console dev/ttyUSBx
2. Set MAC address for the device #xy: <<mac setp 00:26:7b:00:02:XX>>, Control-C
3. Turn power off and on
4. Run eb-console dev/ttyUSBn
5. Type in "mac", you should see the previously entered MAC address
6. If you don't have a DHCP server, you can set an ip address by "ip set 192.168.100.xyz"

Check IOs

1. Go to the tools directory
2. Make io-test
3. Connect IOx and IOy (check that every IO works as input and output)
4. ./io-test dev/ttyUSBx

Check PCIe

1. Try the following tools (WITH DEV/WBM{n}):
   • eb-console dev/wbmn
   • eb-info dev/wbmn
   • eb-ls dev/wbmn

2. Write to internal shared ram and read it back:

   • Get the LM32 shared ram address by eb-ls dev/wbmn
   • Example output: 3.2 0000000000000651:81111444 84000 LM32-RAM-Shared
   • Create a dummy file (which will be written into the ram): dd if=/dev/urandom of=foo bs=4k count=1;
   • Write dummy file to the lm32 shared ram: eb-put dev/wbmn 0x84000 foo
   • Get the data from the shared ram: eb-get dev/wbmn 0x84000/4096 bar
   • Compare both files: cmp foo bar
   • Both files should contain the same data
   • Repeat this test in a loop... (optional)

Check PCIe interrupts

1. The device must be connected with PCI(e) (dev/wbm)
2. Get the Altera-PCIe-MSI-Tgt address (eb-ls dev/wbm0) => "0000000000000651:8a670e73 30000 Altera-PCIe-MSI-Tgt"
3. Run the eca snoop application at the tools directory: ./eca-snoop dev/wbs0 0x30000-0x3ffff
4. Issue an interrupt: eb-write dev/ttyUSB0 0x30000/4 0x1
5. You should see an interrupt in your console now

Optional Steps

Check LEDs

1. Configure everything bidirectional IO as output
2. ./eca-pps dev/ttyUSBx (this tool will output a PPS on every chancel,
   according to your OE setup)
3. You can change the OE setup by eb-write
4. Get the IODIR_HACK slave address by using eb-ls dev/ttyUSBx (Example output: 27.1 0000000000000651:4d78adfd 800 GSI:IODIR_HACK
5. Enable LVDS output: eb-write dev/ttyUSBx 0x800/4 0xff

Check Buttons

1. Go to bel_projects/tools
2. make
3. ./button-game dev/ttyUSBn
4. Press every button, make sure that you saw one event for every button at least. Be aware, that the buttons are not debounced

Check Audio Chip

1. Attack the speaker
2. Make sure that WR is locked
3. Go to bel_projects/modules/nau8811/demo/host-pps-config
4. make
5. Enable the PPS to audio mode: ./eb-pps-config dev/ttyUSB0 -l 30 (-l = loudness; 0 to 100)
6. (Optional) MIC-IN: (turn power on and off if you did the test above)
7. Go to bel_projects/modules/nau8811/demo/lm32-mic-to-spk
8. make all
9. make test
10. Connect an audio cable to "MIC" and Speaker Out at a PC
11. Play some music (youtube, whatever)
12. The Exploder5a should act like an external speaker now

Check Display

1. Connect via JTAG USB
2. Attach the display
3. Go to bel_projects/modules/ssd1325/demo/exploder5_demo
4. make all
5. Upload the demo to lm32: make test
6. Display should show the device status now

Check RAM

1. Create a test file with dd: dd if=/dev/urandom of=put_file bs=33554432 count=1 (32MB; 32*1024*1024)
2. Get the address of the pseudo ram controller by eb-ls dev/ttyUSBx (26 0000000000000651:169edcb7 4000000 Pseudo SRAM)
3. Put the file into the ram by eb-put dev/ttyUSBx 0x4000000 put_file
4. Read back the file from ram by eb-get dev/ttyUSBx 0x4000000/33554432 get_file
5. Compare the files: cmp put_file get_file

Check OneWire Devices

1. Go to: tools/commissioning/onewire-scanner
2. make
3. run application: ./onewire-scanner dev/ttyUSB0
4. There should be 2 controllers and 4 devices (and no unknown devices)

Check Serial Port

1. Connect to RS232
2. Example configuration: (sudo) setserial -g /dev/ttyS0
3. Open with minicom: (sudo) minicom -D /dev/ttyS0
4. Setup should be: Bps/Par/Bits 115200 8N1; Hardware Flow Control : No; Software Flow Control : No
5. You should see the White Rabbit console now

Check 200MHz EE clock

1. Only for WREX2a: Measure the 200MHz clock at the "200MHz" Output pins

Checklist

• White Rabbit/Ethernet
• JTAG (board)
• JTAG (usb)
• USB connection
• LEDs (4xWR, 4xUSER, 1xBASE Power (green), 1xADDON Power (white), 6xLVDSi/o), 8xIO OE, 8xIO ACT)
• Buttons
• IOs
• LVDSi/o
• Display
• Audio
• RAM
• RS232
• OneWire devices
• PCIe + Interrupts
• 200 MHz Clock from WREX2

(Test-)Firmware

Type	rpd	sof	jic	jed (cpld)	date
Exploder5a Test-Image	exploder5_csco_tr.rpd.xz	exploder5_csco_tr.sof.xz	exploder5_csco_tr.jic.xz	exploder5_cpld.jed	Oct 2015