Step-by-step guide to commissioning a new pexaria5:

  1. Place powered-off pexaria5 on ESD-desk , ESD dischare!
  2. Attach wrex2a addon board to baseboard WR1 (WREX2a benötigt ca. 70mA mehr als WREX1)
  3. Insert green SFP into baseboard cage
  4. Connect SFP to WR network
  5. Connect USBCON1 to PC
  6. Remove any pexaria5dbx addon board, bzw. Abstandshalter angeschraubt?
  7. Attach power via 12V input plug (don't power the board yet, just attach the cable), Current limit set to 1000mA
  8. Connect Xilinx programmer to JTAG
  9. Make sure the card has a serial# on it + Add CID-LABEL,
    pex-setup.jpg

  10. Set promo5 adapter to SEL1=1, SEL2=4
    promo14.jpg
  11. Open ISE with syn/gsi_pexarria5/cpld/pexaria5_prog.xise
  12. Process Menu => Implement Top Module
  13. Tools Menu => Impact
  14. Power-on pexaria5 ... then immediately (practice on a working pexaria first):
  15. Double-click Boundary Scan
  16. Control-I, prog1.jed
  17. Operations Menu => Program
  18. Power-off pexaria5

  19. Run 'make' in bel_projects/ip_cores/etherbone-core/hdl/eb_usb_core
  20. Download http://tsl002.acc.gsi.de/releases/cherry/gateware/ oder pexaria5-a2.sof.xz
  21. Decompress it with: 'xz -d pexaria5-a2.sof.xz'
  22. Set promo5 to SEL1=2, SEL2=8
    promo28.jpg
  23. Connect USB-Blaster to JTAG
  24. Power-on pexaria5 power ~
  25. Press and hold switch S3
    pex-s3.jpg
  26. Run: quartus_pgm -c 1 -m jtag -o 'p;pexaria5-a2.sof'26_29_31_35quartus_prog.png
  27. Release S3 , lange warten -> ca. 20 sec bis grüner Text erscheint
  28. Erase USB controller (as root): ./flash-fx2lp.sh -E flash-fx2lp-E.png
  29. Reprogram (reset) the pexaria5: quartus_pgm -c 1 -m jtag -o 'p;pexaria5-a2.sof'
  30. Program the USB controller (as root): ./flash-fx2lp.sh Gelegentlich erscheint die Fehlermeldung "Don't see large enough EEPROM" und PROGRAM wird abgebrochen. Erase und Program sind dann zu wiederholen. 30_flashprg-2_2.png30_flashprg_1_2.png
  31. Reprogram (reset) the pexaria5: quartus_pgm -c 1 -m jtag -o 'p;pexaria5-a2.sof'
  32. Configure the SPI flash chip: eb-config-nv dev/ttyUSBx 10 4, no response if all is ok33_eb-w1-write.png
  33. Format the 1-wire EEPROM in bel_projects/ip_cores/wrpc-sw/tools: eb-w1-write dev/ttyUSBx 0 320 < sdb-wrpc.bin , no response if all is ok, cd ~/Projekte/bel_projects/ip_cores/wrpc-sw/tools | sudo ./eb-w1-write dev/ttyUSB0 0 320 < sdb-wrpc.bin



  34. Power-cycle the pexaria5 / Power ~ 480mA/12V
  35. Program the pexaria5: quartus_pgm -c 1 -m jtag -o 'p;pexaria5-a2.sof'
  36. Flash the FPGA; eb-flash dev/ttyUSBx pci_control.rpd 36_eb_flash.png
  37. Run eb-console dev/ttyUSBx 37_setmac.png
  38. Set MAC address for board #xy: mac setp 00:26:7b:00:04:xy, # exit with crtl-c
  39. Power off the FPGA, remove JTAG
  40. Attach addon board + Add CID Label

  41. Power on the FPGA Power ~530mA /12V, Mit WREX2A sind es ~ 600mA/12V
  42. Run eb-console dev/ttyUSBx 42_eb_console.png
  43. Check 'gui' for Clock Offset <= 10ps for at least 30 seconds. 43_44_ipaddress_cklockphasecheck.png
  44. Confirm that the card receives an IP address , - Erscheint rote IP Meldung BOOTP RUNNING ist die MAC Adresse nicht bekannt bzw. angemeldet. # exit with crtl-c
  45. Attach level Converter (see pic)
  46. Run bel_projects/tools/io-test dev/ttyUSBx 46_io-testcall_ohne_anschluesse.png
  47. Move cable to IO1 and IO3
  48. Rerun io-test
  49. Disconnect cables, and attach to scope
    pex-scope.jpg
  50. Check voltage levels of all 3 LEMOs (0V...3V) and the LVDS (-0.4V...0.4V) outputs
  1. Check 200Mhz at 2. connector lm32-mil-event-jitter.png
  2. Confirm all (4+4) LEDs blink as with the io-test and 2+4 blink to indicate WR network status
  3. Add Bracket + Insert card into a PC
    pex-in-pc.jpg
  4. Run: eb-console dev/wbm0 wbm0mitgui_ipundtimingtest.png
  5. Confirm that 'gui' shows TRACK_PHASE, Sync starts with SYNC_NSEC-> SYNC_PHASE->TRACK_PHASE
  6. Apply gold star to addon- and base-board
    pex-star.jpg

-- WesleyTerpstra - 26 Jun 2014
Topic revision: r20 - 2017-12-05, dbeck
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