Release Asterisk v2 (for miniCS) and updates compatible with SaftLib ( OUTDATED )
%IMAGEGALLERY{size="medium" maxwidth="1000" maxheight="800" sort="name" include="asteriskNode*.*"}%
Asterisk is compatible to the control system releases R3, R4, R5 and R6 The relevant branch in our GIT repository is called
asterisk.
Hardware
Images for Nodes
Table: Images for nodes.
Software for Nodes
Table: Software for nodes (asl73x:/common/export/...).
Table: Images for data master on PEXARIA5A.
Resources
There are four types of I/Os.
- unidirectional single-ended I/O clocked at 125 MHz (1 gpio line connected to FGPA)
- bidirectional single-ended I/O clocked at 125 MHz (2 gpio lines connect to FPGA)
- unidirectional differential I/O clocked at 1 GHz (1 lvds pair connected to FPGA)
- bidirectional differential I/O clocked at 1 GHz (2 lvds pairs connected to FPGA)
The general rules for connecting the I/Os to the resources (ECA, TLU) are determined by the "monster" design. The following rules apply:
- TLU (Timestamp Latch Unit)
- each input is connected to a dedicated TLU fifo
- bidirectional inputs are connected first
- ECA ( Event-Condtion-Action unit)
- all outputs are connected to the ECA
- channel 0: receiving component are 125 MHz outputs (gpio)
- channel 1: receiving component is action queue and MSI. MSI serves to signal events (IRQ) while the event data are stored in the queue until they are retrieved, typically via the host system.
- channel 2: receiving component are 1 GHz outputs (lvds), bidirectional outputs are connected first.
Please note:
- All bidirectional IOs have a output and input connected to the FPGA. The direction is determined via a control line by the FPGA. Hence, each bidirectional IO is connected to the ECA (outgoing) and the TLU (incoming).
- In many cases a differential IO at the front panel is connected to the FPGA using a single ended line and vice versa.
- Changing the direction of bidirectional IO on-the-fly is not supported by the release Asterisk.
| Resource |
EXPLODER |
PEXARIA |
SCU |
VETAR2 + DB2 |
VETAR2 + DB2A |
remark |
| bidi IO 1..N |
Reserve1..8 |
(TTLIO1..3) |
(B1..2) |
N/A |
|
(not configurable on-the-fly) |
| TRIG1 1..8 |
|
|
|
|
|
| TRIG2 1..8 |
|
|
|
|
|
| IN 1..N |
TTL In 1..8 |
TTLIO1 |
B2 |
IN1..2 |
|
|
| ANY In 1..8 |
LVDS1..2 |
|
IN |
|
|
| |
|
|
LVDS1..2 |
|
|
| |
|
|
1x MHDMR |
|
|
| OUT 1..N |
TTL Out 1..8 |
TTLIO2..3 |
B1 |
OUT1..6 |
|
|
| LVDS Out 1..8 |
LVDS3..4 |
|
OUT |
|
|
| ECL Out 1..8 |
|
|
|
|
|
| |
|
|
LVDS3..4 |
|
|
| |
|
|
2x MHDMR |
|
|
| GND |
LVDS Out 9 |
LVDS5 |
N/A |
LVDS5 |
|
|
| TLU 1..N |
TTL In 1..4 |
TTLIO1..3 |
B2 |
LVDS1..2 |
|
|
| ANY In 1..4 |
LVDS1..2 |
|
1x MDHMR |
|
|
| TRIG1 1..4 |
|
|
IN |
|
|
| TRIG2 1..4 |
|
|
|
|
|
| ECA channel 0 1..N |
TTL Out 1..4 |
BaseLEDs 5..8 |
B1 |
TTLOUT1..6 |
|
125 MHz IO |
| LVDS Out 1..4 |
AddonLEDs 1..4 |
|
|
|
|
| ECL Out 1..4 |
|
|
|
|
|
| TRIG(1+2) 1..4 |
|
|
|
|
|
| ECA channel 1 |
USB, lm32 |
PCIe, USB, lm32 |
PCIe, lm32 |
VME, USB, lm32 |
|
Action Q |
| ECA channel 2 1..N |
N/A |
TTLIO1..3 |
N/A |
N/A |
|
1 GHz IO |
| 200 MHz out |
TTL Out 8 |
LVDS3 |
N/A |
LVDS3 |
|
"BuTiS c2" |
| LVDS Out 8 |
|
|
1x MHDMR |
|
|
| ECL Out 8 |
|
|
|
|
|
| 100 kHz + TS out |
N/A |
LVDS4 |
N/A |
LVDS4 |
|
"at the next tone it will be..." |
| |
|
|
1x MHDMR |
|
|
| PPS out |
TTL Out 6 |
N/A |
USERLED 1 |
OUT |
|
use eca-pps if needed |
| LVDS Out 6 |
|
|
|
|
|
| ECL Out 6 |
|
|
|
|
|
| WR ext clkin (10MHZ) |
TTL In 8 |
N/A |
N/A |
IN2 |
|
for grandmaster mode |
| WR ext PPS in |
TTL In 7 |
N/A |
N/A |
IN1 |
|
for grandmaster mode |
| remark |
|
TTLIO1 next to LVDS5 |
|
|
|
|
Versioning
EXPLODER2C
lxyz99:~> eb-info dev/ttyUSB0
Project : exploder_top
Platform : exploder2c +exploder2bdb2 +wrex1
FPGA model : Arria II GX (EP2AGX125DF25C6ES)
Build type : release (asterisk v2)
Build date : Wed Feb 04 17:10:54 CET 2015
Prepared by : CSCO Timing Group <FAIRGSI_Org_CSCOTG_all@gsi.de>
Perpared on : cscotg-build.gsi.de
OS version : Debian GNU/Linux 7.5 (wheezy), kernel 3.2.0-4-amd64
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
85e371c fpga-config-space: include 2.6.32 pci-wb IRQ fix and >=3.10 vme-wb build fix
df24d2f wrpc-sw: include cesar's mininic hang fix
229e96e LM32-Cluster: Fix for systime jumps
dc810a3 drivers: include fixes for interrupts on non-RT systems
6c91e6c monster: eliminate duplicated phase code
PEXARIA5A
Project : pci_control
Platform : pexaria5 +db[12] +wrex1
FPGA model : Arria V (5AGXMA3D4F27C5)
Build type : release (asterisk v1)
Build date : Thu Jul 03 12:25:29 CEST 2014
Prepared by : CSCO Timing Group <FAIRGSI_Org_CSCOTG_all@gsi.de>
Perpared on : cscotg-build.gsi.de
OS version : Debian GNU/Linux 7.5 (wheezy), kernel 3.2.0-4-amd64
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
\n 6c91e6c monster: eliminate duplicated phase code
dbaa402 monster: reset arria5 PLLs for longer (to fix LVDS glitches)
71c4a6d monster: add f_pick to select between alternatives in an expression
930bccf monster: use family constants to eliminate possibility of typo
42e9d0b pexarria5: connect PBS2 as reset button
SCU2
[ruth@scuxl9999 /]# eb-info dev/wbm0
Project : scu_control
Platform : scu +comexpress +wrex1
FPGA model : Arria II GX (EP2AGX125EF29C5)
Build type : release (asterisk v2)
Build date : Wed Feb 04 17:59:31 CET 2015
Prepared by : CSCO Timing Group <FAIRGSI_Org_CSCOTG_all@gsi.de>
Perpared on : cscotg-build.gsi.de
OS version : Debian GNU/Linux 7.5 (wheezy), kernel 3.2.0-4-amd64
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
85e371c fpga-config-space: include 2.6.32 pci-wb IRQ fix and >=3.10 vme-wb build fix
df24d2f wrpc-sw: include cesar's mininic hang fix
229e96e LM32-Cluster: Fix for systime jumps
dc810a3 drivers: include fixes for interrupts on non-RT systems
6c91e6c monster: eliminate duplicated phase code
SCU3 for SaftLib, FG, MFU,
WR is broken
Project : scu_control
Platform : scu3 +comexpress
FPGA model : Arria II GX (EP2AGX125EF29C5)
Build type : developer preview
Build date : Tue Aug 25 12:40:34 CEST 2015
Prepared by : Stefan Rauch <s.rauch@gsi.de>
Perpared on : belpc098
OS version : Ubuntu 14.04.3 LTS, kernel 3.13.0-62-generic
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
8766b02 fg_sw: added MFU to probing code
6f176fe working sdc files for addac, addac2 and diob
151b018 scu_sw: disable fg mode for dacs after use
8acabe4 fg: added ext trigger, dacs are connected to the highest bits
957b4d6 fg_quad: ramp cnt now 32Bit wide
VETAR2A + DB2
[ruth@vme123]$ eb-info dev/wbm0
Project : vetar
Platform : vetar2 +vetar1db2 +wrex1
FPGA model : Arria II GX (EP2AGX125EF29C5)
Build type : release (asterisk v2)
Build date : Wed Feb 04 17:36:47 CET 2015
Prepared by : CSCO Timing Group <FAIRGSI_Org_CSCOTG_all@gsi.de>
Perpared on : cscotg-build.gsi.de
OS version : Debian GNU/Linux 7.5 (wheezy), kernel 3.2.0-4-amd64
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
85e371c fpga-config-space: include 2.6.32 pci-wb IRQ fix and >=3.10 vme-wb build fix
df24d2f wrpc-sw: include cesar's mininic hang fix
229e96e LM32-Cluster: Fix for systime jumps
dc810a3 drivers: include fixes for interrupts on non-RT systems
6c91e6c monster: eliminate duplicated phase code
VETAR2A+DB2A
Project : vetar2a
Platform : vetar2a +vetar1db2a +wrex1
FPGA model : Arria II GX (EP2AGX125EF29C5)
Build type : developer preview
Build date : Tue Dec 16 16:04:26 CET 2014
Prepared by : A. Hahn <a.hahn@gsi.de>
Perpared on : dell-precision-t3610
OS version : Ubuntu 14.04.1 LTS, kernel 3.13.0-43-generic
Quartus : Version 13.1.0 Build 162 10/23/2013 SJ Full Version
\n 4d47cd2 Merge branch 'proposed_master' of https://github.com/stefanrauch/bel_projects into proposed_master
7be5200 vetar2a: Added 4 GPIOs (front LEDs) and a hex to led indicator for vn1 and vn2
8451712 vetar2a: changed info to vetar2a +vetar1db2 +wrex1
ef17271 vetar2a: removed warning (g_gpio_inout)
1dd346b exploder5: newest schematic has clkout connected to USB
- EXPLODER2
- PEXARIA5
- VETAR2
- Obtaining the sources is described in this How-To.
- Building images is described in this How-To.
--
DietrichBeck - 16 Dec 2015
Aikido
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