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You are here: GSI Wiki>TOS/Timing Web>WebChanges (2009-01-09, ProjectContributor)Edit Attach
50 recent changes in TOS/Timing Web retrieved at 13:25 (Local)
TimingSystemGSOverview
Essentials Figure: Building blocks required for a single 'timing event' Bang!. Components of the General Machine Timing (GMT) are shown in blue. Components requ...
r4 - 2018-11-13 - 10:04 by dbeck
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
r6 - 2018-09-27 - 16:40 by dbeck
TimingSystemFEC
How To: WB_FEC This wiki provides information about * WB FEC VHDL module and integration in Bel_Projects * Synthesis of Timing Receiver Gateware with the WB...
r14 - 2018-04-05 - 09:16 by dbeck
TimingSystemHowConfigureDataMaster
Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...
r9 - 2018-03-12 - 10:57 by mkreider
TimingSystemNextReleaseCandidate
"D?" Candidate Release Probably in March 2018. See here. Main.DietrichBeck 01 Mar 2018
r3 - 2018-03-01 - 12:15 by dbeck
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
r6 - 2018-01-30 - 10:55 by dbeck
WRSimulation
WR Simulation How To This How To guide you in the simulation of the WR Core and WR Switch. Setup the Simulation environment You need a ModelSim runnig in your sy...
r5 - 2018-01-24 - 16:40 by cprados
TimingSystemHowOperateClockMaster
Clock Master: How To Operate Introduction This How To is intended for the members of the timing team. The clock master is the White Rabbit Grandmaster Clock of t...
r4 - 2017-12-23 - 10:27 by dbeck
TimingSystemHowConfigureDataMasterR11
Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...
r2 - 2017-12-08 - 09:15 by dbeck
TimingSystemNodesReleaseAsteriskPexaria5Commission
Step by step guide to commissioning a new pexaria5: 1 Place powered off pexaria5 on ESD desk , ESD dischare! 1 Attach wrex2a addon board to baseboard WR1 (W...
r20 - 2017-12-05 - 11:33 by dbeck
TimingSystemHowConfigureDataMasterR3
Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...
r14 - 2017-12-04 - 08:52 by dbeck
TimingSystemHowConfigureDataMasterR10
Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...
r3 - 2017-12-04 - 08:51 by dbeck
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 2017-11-30 - 15:24 by mreese
Wrlldp
How To: WR LLDP This how to describes how to use LLDP in WR Devices. It is not meant to clarify what is LLDP. Info (November 2017): The development is already in...
r4 - 2017-11-15 - 10:38 by dbeck
TimingSystemGPSDO
GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...
r9 - 2017-11-13 - 14:26 by dbeck
TimingSystemDBusInfo
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
r16 - 2017-09-15 - 11:10 by mreese
TimingSystemNodesSnapshotApr2017
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
r5 - 2017-05-05 - 09:18 by dbeck
TimingSystemHowSoftCPULM32Command
How To: LM32 Soft CPU Send a Command to a LM32 Soft CPU Introduction This how to demonstrates how to send a command to LM32 Soft CPU. This how to demonstrates ...
r2 - 2017-03-28 - 10:50 by dbeck
TimingSystemHowSoftCPUUseDevicebus
How To: LM32 Soft CPU Using MIL Devicebus Introduction This how to demonstrates how to access a device on a MIL Devicebus connected to the SCU ("MIL piggy"). A...
r2 - 2017-03-28 - 10:49 by dbeck
TimingSystemHowSoftCPUAccessLM32SharedMemWB
How To: LM32 Soft CPU Accessing a LM32 Soft CPU via shared memory and Wishbone Introduction This how to demonstrates how to access the LM32 Soft CPU via Shared...
r2 - 2017-03-28 - 10:48 by dbeck
TimingSystemHowSoftCPUAccessOtherWB
How To: LM32 Soft CPU Accessing Another SoC Wishbone Device Introduction This how to demonstrates how to access another Wishbone device on the same SoC from th...
r2 - 2017-03-28 - 10:47 by dbeck
EXPLODER5A
Figure 1: A complete exploder5a module (top view). Main.AlexanderHahn 15 Jul 2015
r2 - 2016-02-23 - 16:03 by dbeck
TimingSystemNodesReleaseAsteriskVetar2aCommission
Vetar2a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Needed components for each...
r11 - 2015-10-22 - 16:44 by ahahn
FirmwareID
Main.MathiasKreider 07 May 2015 Getting Information about the Firmware on a device Firmware IDs The eb info tool was used to read out the build id ROM, providin...
r3 - 2015-05-11 - 11:06 by mkreider
TimingSystemNodesReleaseR1VETAR2
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
r22 - 2014-11-06 - 17:39 by dbeck
TimingSystemLSAInterface
FESA Properties for DataMaster Class (current version running on vmla03) Global Interface (Device Name MCS_DM_GLOBAL) Setting Properties * Command * dataM...
r10 - 2014-10-22 - 11:37 by mkreider
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
NEW - 2014-09-29 - 13:54 by dbeck
TimingSystemDocumentsFTRNFeatures
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
r13 - 2014-09-25 - 22:07 by dbeck
TimingSystemNodesReleaseR1Exploder2C
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
r14 - 2014-07-17 - 10:24 by dbeck
TimingSystemNodesReleaseR1
Nodes: Release R1 Overview rpd ...
NEW - 2014-07-15 - 17:04 by dbeck
TimingSystemNodesReleaseR1SCU2
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
r3 - 2014-07-15 - 16:56 by dbeck
TimingSystemNodesReleaseR1PEXARIA5
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
r16 - 2014-07-15 - 16:52 by dbeck
TimingSystemDocumentsBlackCat1
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
r4 - 2014-07-15 - 16:50 by dbeck
TimingSystemDocumentsSIXIO2
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
r5 - 2014-07-15 - 14:57 by dbeck
TimingSystemBuTiSReceiver
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
r9 - 2014-07-15 - 13:12 by dbeck
TimingSystemManagementMaster
Management Master Configuration ... to be done... Main.DietrichBeck 03 Apr 2014
r2 - 2014-07-15 - 13:12 by dbeck
TimingSystemHowConfigureDataMasterR1
Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...
r3 - 2014-07-10 - 10:42 by dbeck
TimingSystemDocumentsPEXARIA5DB1
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
r4 - 2014-05-05 - 09:33 by dbeck
TimingSystemDocumentsAddOnBoardFeatures
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
r11 - 2013-11-01 - 09:15 by dbeck
GSITimingTeam
FAIR Timing/GSI Timing Team Core members of the GSI Timing Team are: T.Fleck C.Prados S.Rauch M.Kreider Further leading actors within the GSI controls group are U...
r3 - 2009-03-05 - 08:55 by TiborFleck
NetworkTopologyInterfaces
* chap2.pdf: Chapter2 Topology Main.CesarPrados 03 Mar 2009
r2 - 2009-03-04 - 14:52 by TiborFleck
WebAtom
GSI Wiki's TOS/Timing web
NEW - 2009-01-09 - 13:00 by ProjectContributor
NEW - 2009-01-09 - 13:00 by ProjectContributor
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" else="GSI Wiki's TOS/Timing web"}% /TOS/Timing
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NEW - 2007-05-09 - 23:29 by ProjectContributor
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