Doomsday Release (DEPRECATED)

Previous releases are Asterisk, Balloon and Cherry.

This release is replaced by Enigma.

New features and bug-fixes in Doomsday Release

• 2018-Apr-17: [v4.0.4] Experimental kernel 4.x support
• 2018-Apr-17: [v4.0.4] Saftlib v1.4.0
• 2018-Apr-17: [v4.0.4] Display support (SCU example: $simple-display dev/wbm0 -s "Test" -d 1)
• 2018-Apr-17: [v4.0.4] Function Generator bugfixes and new functions
• 2018-Apr-17: [v4.0.4] Removed syslog from wrpc-sw
• 2018-Apr-17: [v4.0.4] Added PMC und AMC form factor
• 2018-Jun-26: [v4.0.5] Saftlib v.1.4.1
• 2018-Jun-26: [v4.0.5] Firmware update for mTCA ARM
• 2018-Jun-26: [v4.0.5] Function generator bugfixes ("SCU DREQ CLEAR")
• 2018-Jun-26: [v4.0.5] Improved eb-reset, added support for LM32 reset
• 2018-Jun-26: [v4.0.5] FPGA-CONFIG-SPACE update, pcie_wb supports PMC/PCI now
• 2019-Jan-29: [v4.0.6]
  • Function generator bugfixes (LM32 firmware)
  • hotfix 2019-nov-12: disabled 'socat'

Known Issues of Doomsday Release

• 2018-Apr-17: Timing requirements not met during synthesis
• 2018-Apr-17: Sometimes WR port of node remains down after power cycle of node AND WR switch Issue
• 2018-Apr-17: Flashing devices is a touchy Issue
  • https://github.com/GSI-CS-CO/bel_projects/issues/83
  • https://github.com/GSI-CS-CO/bel_projects/issues/82
  • To avoid bricking the device, it is highly recommended to stop "kill" all host system software and halt all 'user' lm32 cores prior to flashing.
• 2019-Aug-12:
  • Doomsday is incompatible with all SCU ramdisks of build date 2019-08-12 and newer
  • Frontends requiring Doomsday shall use the PXE configuration 'scuxl.doomsday' instead of 'scuxl'

Releases

Release Name	Date	Release Version	Gateware	Etherbone	Saftlib	FESA	Type	GIT hash
Doomsday Alpha	2018-Jan-21	4.0.0	4.0.0	2.1.0	1.2.3		alpha
Doomsday V0.0	2018-Apr-04	4.0.0	4.0.0	2.1.0	1.3.0		release candidate	6e0ad9e
Doomsday V0.1	2018-Apr-05	4.0.1	4.0.1	2.1.0	1.4.0		release candidate	9b74673
Doomsday V0.2	2018-Apr-06	4.0.2	4.0.2	2.1.0	1.4.0		release candidate	cc0dc49
Doomsday V0.3	2018-Apr-16	4.0.3	4.0.3	2.1.0	1.4.0		release candidate	2fe7692
Doomsday V0.4	2018-Apr-17	4.0.4	4.0.4	2.1.0	1.4.0		outdated release	14ffc1a
Doomsday V0.5	2018-Jun-26	4.0.5	4.0.5	2.1.0	1.4.1		outdated release	23f29bbf
Doomsday V0.6	2019-Jan-29	4.0.6	4.0.5	2.1.0	1.4.1		release	bb1dd75

Table: Version matrix.

Timing Receiver Nodes

Gateware Images

• Doomsday V0/V.4.0.6 for the Doomsday gateware/firmware/software are available here.
• Nightly builds for the Doomsday gateware/firmware/software are available here.

FPGA images are stored locally for each form factor in a flash. See here for flash instructions.

Software

Type	Path in SL7 Servers	Comment
build environment for software	N/A	provided by FEE
run-time system for timing	/common/export/timing-rte/tg-doomsday-v< VERSION >	nfsinit: 20_timing-rte -> ../global/timing-rte-tg-doomsday-v< VERSION > Example: 20_timing-rte -> ../global/timing-rte-tg-doomsday-v4.0.5

Table: Software (drivers, etherbone and saftlib) are deployed to ACO FECs via nfs-init. This is triggered by creating symbolic links.

How-To check FEC is booting from Doomsday Run Time Environment

OS

[ruth@scuxl0815 ~]# uname -r
3.10.101-rt111-scu01

[ruth@scuxl0815 ~]# cat /etc/os-release
GSI embedded release 7 (build 2019-05-28) // or older

In case of a different kernel, please contact CSCOIN.

Etherbone

[ruth@scuxl0815 ~]# eb-mon -e dev/wbm0
etherbone 2.1.0 (balloon-5-gba955bc): Feb 10 2017 13:09:27 / built by ahahn on Apr 17 2018 11:38:02 with asl742.acc.gsi.de running CentOS Linux release 7.4.1708 (Core) 

Saftlib and Gateware

[ruth@scuxl0815 ~]# saft-ctl bla -fij
saftlib source version                  : saftlib 1.4.1 (v1.4.0-3-ga6437c6): Jun 07 2018 12:14:55
saftlib build info                      : built by ahahn on Jun  8 2018 13:14:23 with asl742.acc.gsi.de running CentOS Linux release 7.4.1708 (Core) 
devices attached on this host   : 1
  device: /de/gsi/saftlib/tr0, name: tr0, path: dev/wbm0, gatewareVersion : 4.0.6
  --gateware version info:
  ---- Mon Jan 28 16:35:14 CET 2019
  ---- Doomsday-v4.0.6
  ---- Arria II GX (ep2agx125ef29c5)
  ---- Debian GNU/Linux 8.10 (jessie), kernel 3.16.0-4-amd64
  ---- scu2 +comexpress +wrex1
  ---- Jenkins Nightly Build <csco-tg@gsi.de>
  ---- tsl002.acc.gsi.de
  ---- scu_control
  ---- Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
  ---- zenith-2003

Info Files In case of trouble, the following info files on the run-time system itself might be informative.

[ruth@scuxl0815 ~]# cat /etc/os-release
GSI embedded release 7 (build 2017-04-06)
or newer until
GSI embedded release 7 (build 2019-05-28)

If your ramdisk is newer, it will not be compatible with this release

Timing Run Time Environment

[ruth@scuxl0815 ~]# cat /etc/timing-rte_buildinfo 
GSI Timing RTE 08-06-2018_13-14-43 
Compiled by ahahn using ./build-rte.sh on asl742.acc.gsi.de - Linux  3.10.0-862.2.3.el7.x86_64
CI_CD Project
 - https://github.com/GSI-CS-CO/ci_cd.git
 -  master*@bf0c466
BEL_PROJECTS
 - https://github.com/GSI-CS-CO/bel_projects.git
 - doomsday-v4.0.5@23f29bb
Last Commits in repo:
23f29bb fpga-config-space: added pmc/pci support
02ca0d4 saftlib: v1.4.1
e13be6a Merge pull request #95 from GSI-CS-CO/scu_dreq_clear
d80f22d Merge pull request #94 from GSI-CS-CO/eb-tools_dietrich_2018-may-04
bc2be39 scu_sw: send broadcast only to active sios

How-To Test a Timing Receiver running Doomsday

See this How-To

Bitstreams

Types of Bitstream	Platform	Description	How to Flash or Program
rpd	Altera	Raw Programming Data File. This file contains the TR Gateware. It's used to write the gateware into the flash memory of the TR. It is persistent	eb-flash
sof	Altera	SRAM Object File. This file contains the TR Gateware. It's used to write to program the FPGA. It is not persistent	Quartus Programmer
jic	Altera	JTAG Indirect Configuration File. This file contains the TR Gateware. It's used to program the FPGA. It is not persistent	Quartus Programmer
jed	Xilinx	This file contains the special Gateware for the CPLD on the TR. It is persistent	Xilinx Programmer

Supported Hardware

The hardware supported in this Release:

Form Factor	Carrier	WR	add-on	Commissioning	Remark
standalone	EXPLODER5A	WREX1/WREX2A	EXPLODER5ADB2	click
PCIe	PEXARIA5XX	WREX1	PEXARIA5DBYY	click	"fixed" PEXARIA5 boards are compatible
SCU2	SCU2	WREX1	(MIL)
SCU3	SCU3	on-board	(MIL)
VME	VETAR2A	WREX1	VETAR1DB2A	click
AMC	tr-amc	on-board	N/A
PMC	tr-pmc	on-board	N/A

Table: Hardware for nodes.

Data Master

Sources for Data Master images and software are part of the GIT repository in dedicated branches.

Getting the sources code of the Doomsday Release from our GIT Repository

If you want to check the source code this Release is in the branch "doomsday" in bel_projects.

git clone git@github.com:GSI-CS-CO/bel_projects.git  // try 'git clone https://github.com/GSI-CS-CO/bel_projects' if not using public/private key authentification
cd bel_projects
./autogen.sh 
git checkout doomsday

More Information

• building and deployment the Timing Run-Time Environment, see here
• building and deployment of software and drivers for various types of linux boxes (including SCU), see here and here
• flashing timing receivers with new images (including SCU), see here
• some hints for FECs, see here

-- DietrichBeck - 01 Mar 2019