Balloon Release (OUTDATED)

The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integrate your development with our firmware you need a FEC flashed with the Release Firmware. Below you can find the links to the firmware and how to flash a FEC.

New features and bug-fixes in Balloon Release

• New WR logging and monitoring capabilities
• Add to WR PPSI the Peer Delay Sync mechanism
• General Bug fixes of the wrpc-sw and wr-core
• Fixed all the FPGA timing constrains problems
• New Timing Run-Time Environment building and deployment system
• Fixed flash controller
• Added access to separate Message Signalled Interrupt (MSI) bus subsystem to all SoC devices
• Increased DM/ECA timestamp resolution to native 1 ns
• Increased number of usable DM CPU cores to 8
• DM now supports core/schedule synchronization via MSI
• Updated ECAv1 to ECAv2
• New ECAv2 tools are now available: saft-ctl, saft-io-ctl, saft-clk-gen, ... (tutorial)

Known Issues of Balloon Release

• The WR Switches losses Ethernet packets under a wide range of bandwidth and network topologies, report
• Single 200ns drifts of the synchronization, only detected in FECs
• Overrun of the WR End Point buffer under certain traffic conditions
• The GSI VME Vetar FEC and CERN VME Svec have problems working in the same rack bug report
• Jumps of 8ns in the SERDES output bug report

Supported Hardware

The hardware supported in this Release:

Form Factor	Carrier	WR	add-on	Commissioning	Remark
standalone	EXPLODER5A	WREX1/WREX2A	EXPLODER5ADB2	click
PCIe	PEXARIA5A	WREX1	PEXARIA5DB1/2	click	"fixed" PEXARIA5 boards are compatible
SCU2	SCU2	WREX1	(MIL)
SCU3	SCU3	on carrier	(MIL)
VME	VETAR2A	WREX1	VETAR1DB2A	click

Table: Hardware for nodes.

Timing Receiver Nodes

Gateware Images

Type	FPGA Bitstream	CPLD Bitstream	date
PEXARIA5A	exploder5_scso_tr.rpd, sof, jic	pexaria5-cpld.jed	2016-Dec-31
EXPLODER5A	pcie_control.rpd, sof, jic	exploder5-cpld.jed	2016-Dec-31
SCU2	scu_control2.rpd, sof, jic	--	2016-Dec-31
SCU3	scu_control3.rpd, sof, jic	--	2016-Dec-31
VETAR2A	vetar2a.rpd, sof, jic	--	2016-Dec-31

Table: Bitstream tarballs for the Timinmg Receiver Nodes.

Nightly builds for the balloon gateware/firmware/software are available here

Info about the FPGA and CPLD Bitstreams, here

Software

Type	Path in SL7 Servers	Comment
build environment for software	N/A	provided by CSCOFE
run-time system for timing	/common/export/timing-rte/R8-balloon_0	nfsinit: 20_timing-rte -> ../global/timing-rte-R8-balloon_0

Table: Software.

For the complete FECs stack you need also FESA. FESA 4.0 is the compatible release for Balloon.

If you have a local installation re-install please Etherbone and Saftlib software from bel_projects, and remember that the ECA-tools are deprecated.

make etherbone-install
make etherbone-saftlib
make tools-install

For building and deployment the Timing Run-Time Environment please checkout the wiki where it is explain how to checkout the software and build it. Remember that you have to checkout the balloon release.

Data Master

Type	FPGA Bitstream	Firmware	tool	remark	date
PEXARIA5A	ftm.rpd, sof, jic	ftm.bin	ftm-ctl	Check!	2016-Dec-31

Table: Images for data master on PEXARIA5A.

Info about the FPGA and CPLD Bitstreams, here

Getting the sources code of the Balloon Release from our GIT Repository

If you want to check the source code this Release is in the branch "ballon" in bel_projects.

git clone --recursive git@github.com:GSI-CS-CO/bel_projects.git
git checkout balloon
git submodule init
git submodule update --recursive

How to...

Know if my FEC is booting from Balloon Run Time Environment

Possibility 1: View Info Files

OS

[ruth@scuxl0815 ~]# cat /etc/os-release 
GSI embedded release 7 (build 2016-08-11)

If that file does not exist or includes different information, please contact CSCOIN.

Timing Run Time Environment

[ruth@scuxl0815 ~]# cat /etc/timing-rte_buildinfo 
GSI Timing RTE 22-12-2016_09-15-48 
Compiled by dbeck using ./build-rte.sh on asl742.acc.gsi.de - Linux  3.10.0-327.28.3.el7.x86_64
CI_CD Project
 - https://github.com/GSI-CS-CO/ci_cd.git
 - master*@3a0d1e8
 - Dirty
BEL_PROJECTS
 - https://github.com/GSI-CS-CO/bel_projects.git
 - balloon@dec8dd0
 - Nothing to commit

Most important information to check:

Bel Projects	CI_CD
balloon@dec8dd0	master*@3a0d1e8

Possibility 2: Using Tools

OS

[ruth@scuxl0815 ~]# uname -r
3.10.101-rt111-scu01

In case of a different kernel, please contact CSCOIN.

Etherbone and Saftlib Version

[ruth@scuxl0815 ~]# eb-mon -e dev/wbm0
etherbone 2.1.0 (v2.1.0-4-g809617b): Apr 29 2016 02:26:04 / built by dbeck on Dec 22 2016 09:14:50 with asl742.acc.gsi.de running CentOS Linux release 7.2.1511 (Core)

[ruth@scuxl0815 ~]# saft-ctl bla -fi
saftlib source version                  : saftlib 1.0.9 (v1.0.9-1-g246e15d): Dec 13 2016 16:39:35
saftlib build info                      : built by dbeck on Dec 22 2016 09:15:42 with asl742.acc.gsi.de running CentOS Linux release 7.2.1511 (Core) 

Most important information to check:

Etherbone Version	Saftlib Version
v2.1.0-4-g809617b	v1.0.9-1-g246e15d

Know if I Have a Valid Firmware

[ruth@scuxl0815 ~]# eb-info dev/wbm0
Project     : scu_control
Platform    : scu3 +comexpress
FPGA model  : Arria II GX (EP2AGX125EF29C5)
Source info : balloon-1319
Build type  : Balloon_release
Build date  : Sat Dec 31 04:46:01 CET 2016
Prepared by : Jenkins Nightly Build <csco-tg@gsi.de>
Prepared on : tsl002.acc.gsi.de
OS version  : Debian GNU/Linux 8.6 (jessie), kernel 3.16.0-4-amd64
Quartus     : Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

  dec8dd0 ftm-ctl: added solid generic status function for FESA class
  3dea586 ftm: bumped version numbers
  e67587c Merge branch 'balloon' of github.com:GSI-CS-CO/bel_projects into balloon
  3c7ad89 build:change the FPGA version in ArriaV devices
  0c9fa34 saftlib: updated to v1.0.9

Most important information to check:

Build type	Source Info	Last Commit	Build Data
Balloon_release	balloon-1319	dec8dd0	>= 21/12/2016

Test a Timing Receiver running Balloon

If you need timing events for integration purposes or testing, connect your FEC in the Integration System and you will get events from the Balloon-Data Master.

Another option is to inject events from the Run Time System, this related how-to can help you.

Bitstreams

Types of Bitstream	Platform	Description	How to Flash or Program
rpd	Altera	Raw Programming Data File. This file contains the TR Gateware. It's used to write the gateware into the flash memory of the TR. It is persistent	eb-flash
sof	Altera	SRAM Object File. This file contains the TR Gateware. It's used to write to program the FPGA. It is not persistent	Quartus Programmer
jic	Altera	JTAG Indirect Configuration File. This file contains the TR Gateware. It's used to program the FPGA. It is not persistent	Quartus Programmer
jed	Xilinx	This file contains the special Gateware for the CPLD on the TR. It is persistent	Xilinx Programmer

More Information

• building and deployment of software and drivers (including SCU), see here and here
• flashing timing receivers with new images (including SCU), see here
• some hints for FECs, see here