Cherry Release V4 (OUTDATED)
The
Cherry Release is
partly compatible with the the
Balloon release.
- ECA et al should be compatible
- But ...
- there are changes in the White Rabbit core that may lead to incorrect reporting of the WR status.
- the Wishbone crossbar architecture has changed, which might affect cases where resources are addressed concurrently
- ...
When using FESA3 4.3.1 on a FEC, it is
highly recommended to upgrade the FECs gateware from
Balloon to
Cherry .
New features and bug-fixes in Cherry Release
- upgrade to WR 4.1
- modified crossbar architecture
- general Bug fixes of the wrpc-sw and wr-core
- minor fixes and improvements of command line tools
- [Cherry v4]: added support for timing message with format ID 0x1
- [Cherry v4]: changed MasterFunctionGenerator interface replacing vector<bool> with vector<int>
- [Cherry v4]: saftd -> timing receivers will be named as tr0, tr1, ..., tr{n} from now on (the default name "baseboard" will not be used anymore)
Known Issues of Cherry Release
- The WR Switches losses Ethernet packets under a wide range of bandwidth and network topologies, report
- support for "bursts" not yet integrated (a feature requested by beam instrumentation)
- support for features requested by Experiment Electronics not yet integrated
Supported Hardware
The hardware supported in this Release:
Table: Hardware for nodes.
Timing Receiver Nodes
Gateware Images
Nightly builds for the cherry gateware/firmware/software are available
here
Info about the FPGA and CPLD Bitstreams,
here
Software
Type |
Path in SL7 Servers |
Comment |
build environment for software |
N/A |
provided by CSCOFE |
run-time system for timing |
/common/export/timing-rte/tg-cherry-v4 |
nfsinit: 20_timing-rte -> ../global/timing-rte-tg-cherry-v4 |
run-time system for timing |
/common/export/timing-rte/tg-cherry-v4-meltdown |
nfsinit: 20_timing-rte -> ../global/timing-rte-tg-cherry-v4-meltdown |
Table: Software. The
meltdown build has been prepared after meltdown patches had been applied to the ASL cluster.
For the complete FECs stack you need also FESA.
FESA 4.3.1 is the compatible release for Cherry.
If you have a local installation re-install please Etherbone and Saftlib software from
bel_projects.
git checkout cherry
./fix-git.sh
make etherbone; (optional: make etherbone-install)
make saftlib; (optional: make saftlib-install)
make tools; (optional: make tools-install)
For building and deployment the Timing Run-Time Environment please checkout the
wiki where it is explained how to checkout the software and build it. Remember that you have to checkout the cherry release.
Data Master
Sources for Data Master images and software are part of the GIT repository in dedicated branches.
Getting the sources code of the Cherry Release from our GIT Repository
If you want to check the source code this Release is in the branch "cherry" in
bel_projects.
git clone --recursive git@github.com:GSI-CS-CO/bel_projects.git
git checkout cherry
./fix-git.sh
./install-hdlmake
How to...
Know if my FEC is booting from Cherry Run Time Environment
Possibility 1: View Info Files
OS
[ruth@scuxl0815 ~]# cat /etc/os-release
GSI embedded release 7 (build 2017-04-06)
If that file does not exist or includes different information, please contact CSCOIN.
Timing Run Time Environment
[root@scuxl0143 ~]# cat /etc/timing-rte_buildinfo
GSI Timing RTE 11-12-2017_16-37-50
Compiled by ahahn using ./build-rte.sh on asl740.acc.gsi.de - Linux 3.10.0-693.5.2.el7.x86_64
CI_CD Project
- https://github.com/GSI-CS-CO/ci_cd.git
- master*@faec597
BEL_PROJECTS
- https://github.com/GSI-CS-CO/bel_projects.git
- cherry_v4@b4b4ffb
- Nothing to commit
Last Commits in repo:
b4b4ffb saftlib: v1.2.0
25274b9 Merge pull request #55 from GSI-CS-CO/eb-reset_dietrich_2017-dec-01
9813835 eb-reset: add eb tool 'eb-reset'.
9c1601e saftlib: added support for timing message with format ID 0x1
ffaa50d Merge pull request #54 from GSI-CS-CO/ifa_fg
Most important information to check:
OS
[ruth@scuxl0815 ~]# uname -r
3.10.101-rt111-scu01
In case of a different kernel, please contact CSCOIN.
Etherbone and Saftlib Version
[ruth@scuxl0815 ~]# eb-mon -e dev/wbm0
etherbone 2.1.0 (balloon-3-gcb8c807): Feb 10 2017 13:09:27 / built by ahahn on Dec 11 2017 16:36:56 with asl740.acc.gsi.de running CentOS Linux release 7.4.1708 (Core)
[ruth@scuxl0815 ~]# saft-ctl bla -fi
saftlib source version : saftlib 1.2.0 (v1.2.0): Dec 11 2017 13:28:26
saftlib build info : built by ahahn on Dec 11 2017 16:37:44 with asl740.acc.gsi.de running CentOS Linux release 7.4.1708 (Core)
Most important information to check:
Know if I Have a Valid Firmware
[ruth@scuxl0815 ~]# eb-info dev/wbm0
Project : exploder5_csco_tr
Platform : exploder5 +db[12] +wrex2
FPGA model : Arria V (5agxma3d4f27i3)
Source info : cherry-1653
Build type : Cherry_Release
Build date : Thu Jan 11 15:08:08 CET 2018
Prepared by : Jenkins Nightly Build <csco-tg@gsi.de>
Prepared on : tsl002.acc.gsi.de
OS version : Debian GNU/Linux 8.10 (jessie), kernel 3.16.0-4-amd64
Quartus : Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
b4b4ffb saftlib: v1.2.0
25274b9 Merge pull request #55 from GSI-CS-CO/eb-reset_dietrich_2017-dec-01
9813835 eb-reset: add eb tool 'eb-reset'.
9c1601e saftlib: added support for timing message with format ID 0x1
ffaa50d Merge pull request #54 from GSI-CS-CO/ifa_fg
Most important information to check:
Test a Timing Receiver running Cherry
If you need timing events for integration purposes or testing, connect your FEC in the
Integration System
and you will get events from the Cherry-Data Master.
Another option is to inject events from the Run Time System, this related
how-to can help you.
Bitstreams
Types of Bitstream |
Platform |
Description |
How to Flash or Program |
rpd |
Altera |
Raw Programming Data File. This file contains the TR Gateware. It's used to write the gateware into the flash memory of the TR. It is persistent |
eb-flash |
sof |
Altera |
SRAM Object File. This file contains the TR Gateware. It's used to write to program the FPGA. It is not persistent |
Quartus Programmer |
jic |
Altera |
JTAG Indirect Configuration File. This file contains the TR Gateware. It's used to program the FPGA. It is not persistent |
Quartus Programmer |
jed |
Xilinx |
This file contains the special Gateware for the CPLD on the TR. It is persistent |
Xilinx Programmer |
- building and deployment of software and drivers (including SCU), see here and here
- flashing timing receivers with new images (including SCU), see here
- some hints for FECs, see here