HELP
, SEND
, SPI
, etc, followed by (optional) arguments or sub commands
<Keyword, 3-5 letters, (capital letters)> <Message>
RECV
followed by the sent command keyword and the 'result'
DEBG <debug level>
, <debug level> > 0 RECV
<literal acknowledge>*
ERRx
in case of an error ERRx <Error number> <Error description>
ERRx <Error number> <Error description> *** "<Additional Information>"
ERRx "<Command>" <Error number> <Error description>
ERRx "<Command>" <Error number> <Error description> *** "<Additional Information>"
G
: global errors
A
: api errors, e.g. typos, wrong arguments, inputs, syntax, out of limits, etc.
C
: CAN related global errors
M
: CAN related message box errors
T
: I²C errors, Two-Wire-Interface
U
: undefined
HELP
:
will give an overview list of available commands, e.g. :
RECV HELP --- available commands are:
RECV HELP --- SEND : send can message
RECV HELP --- SEND CAN-ID ID-Range [RTR <nBytes> D0 .. D7]
RECV HELP --- SUBS : unsubscribe can id/mask
RECV HELP --- SUBS CAN-ID ID-Range
RECV HELP --- USUB : unsubscribe can id/mask
RECV HELP --- USUB CAN-ID ID-Range
RECV HELP --- RGWR : write register
RECV HELP --- RGWR <Register> <Value>
RECV HELP --- RGRE : read register
RECV HELP --- RGRE <Register>
RECV HELP --- RADC : AVR ADCs
RECV HELP --- RADC [<ADC Channel>]
RECV HELP --- OWAD : 1-wire ADC
RECV HELP --- OWAD [ID [flag_conv [flag_init]]]
RECV HELP --- OWDS : 1-wire double switch
RECV HELP --- OWDS [ID]
RECV HELP --- INIT : (re)init of system
RECV HELP --- OWLS : 1-wire list devices
RECV HELP --- OWLS [<Family Code>]
RECV HELP --- OWSS : 1-wire single switch ([ID] not implemented)
RECV HELP --- OWSS [ID]
RECV HELP --- RSET : reset via watchdog
RECV HELP --- PING :
RECV HELP --- OWTP : 1-wire temperature
RECV HELP --- OWTP [ID [flag_conv [flag_init]]
RECV HELP --- OWTP <command_keyword> [arguments]]
RECV HELP --- OWSP : one-wire set active pins/bus mask
RECV HELP --- OWSP <bus mask>
RECV HELP --- CANT : CAN send message
RECV HELP --- CANT CAN-ID ID-Range [RTR <nBytes> D0 .. D7]
RECV HELP --- CANS : CAN subscribe
RECV HELP --- CANS CAN-ID ID-Range
RECV HELP --- CANU : CAN unsubscribe
RECV HELP --- CANU CAN-ID ID-Range
RECV HELP --- DBGL : set/get debug level
RECV HELP --- DBGL [level]
RECV HELP --- DBGM : set/get debug system mask
RECV HELP --- DBGM [mask]
RECV HELP --- JTAG : set/get JTAG availability, switch off/enable 4 more ADC channels
RECV HELP --- JTAG [0|1]
RECV HELP --- HELP : help
RECV HELP --- HELP [CMND]
RECV HELP --- HELP <mode>
RECV HELP --- OWRP : 1-wire read active pins/bus mask
RECV HELP --- DEBG : set/get debug level and mask
RECV HELP --- DEBG [level [mask]]
RECV HELP --- PARA : parasitic device presence test
RECV HELP --- SHOW : show (internal) settings
RECV HELP --- SHOW [key_word]
RECV HELP --- OWSA : 1-wire API settings
RECV HELP --- OWSA <command_key_word> [arguments]
RECV HELP --- TWIS : I2C access
RECV HELP --- TWIS <0|1> <I2C address> <data length> <byte1 ... byte8>
RECV HELP --- I2C : I2C access
RECV HELP --- I2C <0|1> <I2C address> <data length> <byte1 ... byte8>
RECV HELP --- RLTH : relay threshold
RECV HELP --- RLTH [command_key_word] <value>
RECV HELP --- SPI : experimental SPI master (slave)
RECV HELP --- SPI [data]
RECV HELP --- SPI <cmd> <arguments>
RECV HELP --- GNWR : waveform generator write data
RECV HELP --- GNWR <address> <data>
RECV HELP --- GNRE : waveform generator read data
RECV HELP --- GNRE <address>
RECV HELP --- OW8S : 1-wire octal switches
RECV HELP --- OW8S [ID [value]]
RECV HELP --- VERS : code version
HELP <command>
Keyword | Action | Format | Description![]() |
Comments |
---|---|---|---|---|
SEND CANT |
Send CAN Message | SEND <CAN Message-ID> <ID-Range> [<RTR> <Length> <Data0 ... Data7>] CANT <CAN Message-ID> <ID-Range> [<RTR> <Length> <Data0 ... Data7>] response: RECV <MOB-number> <CAN Message-ID> <ID-Range> [<RTR> <Length> <Data0 ... Data7>] future response: RECV <CAN Message-ID> <ID-Range> [<RTR> <Length> <Data0 ... Data7>] |
Message-ID: CAN Message Identifier (hex) ID-Range: used as mask on Message IDs (hex) RTR: sets Remote Transmission Request Mode Length: number of data bytes to send (max: 8) Data 0...7: 0 to 8 data bytes (hex) MOB-number: index of receiving MOB (Message Object Blocks) in CAN controller |
|
CAN | CAN commands | CAN <sub command> [ <arguments>> ... ] response: ... |
Replacing above commands by sub commoands | TODO: |
SUBS CANS |
Subscribe to Message-IDs | SUBS <CAN Message-ID> <ID-Range> CANS <CAN Message-ID> <ID-Range> response: nothing |
Subscribe to react on (a range of) CAN Messages Message-ID: CAN Message Identifier (hex) ID-Range: used as mask on Message IDs (hex) |
TODO: look to code, has to be clarified |
USUB CANU |
Unsubscribe from Message-IDs | USUB <CAN Message-ID> <ID-Range> CANU <CAN Message-ID> <ID-Range> response: nothing |
Unsubscribe from reacting on (a range of) CAN Messages Message-ID: CAN Message Identifier (hex) ID-Range: used as mask on Message IDs (hex) |
TODO: look to code, has to be clarified |
SPI
command set allows to operate the Serial Peripheral Interface SPI interface of the HadCon(2)'s microcontroller, (currently "only") as a master.
It sends data in atomic chunks of bytes via the MOSI
pin to slave devices and receives via the MISO
pin the responses.
This happens in a buffered mode, so that multiple bytes can be send and received at once.
SPI write dc 7f 8f8fb4 0123456789abcdef be
SPI dc 7f 8f8fb4 0123456789abcdef be
write
command includes the following steps: dc 7f 8f 8f b4 01 23 45 67 89 ab cd ef be
SPI read
SPI show_read_buffer 3 1
SPI show_read_buffer 6
SPI show_read_buffer
TheSPI purge_read_buffer
// optionally
SPI purge_write_buffer// optionally
SPI add dc 7f SPI add 8f8fb4// repeat until write buffer is full
SPI add 0123456789abcdef//
SPI add be//
SPI show_write_buffer// optionally
SPI write_buffer SPI write_buffer// e.g. repeat it, if auto_purge is OFF
SPI write_buffer 02// only activate second chip select pin, by masking it with 0x02
write_buffer
command includes all remaining necessary steps: Reading: see Basic OperationSPI write dc 7f 8f8fb4 0123456789abcdef be SPI write_buffer
// e.g. repeat it, if auto_purge is OFF
... SPI write_buffer SPI write_buffer 02// only activate 2nd chip select pin, by masking it with 0x02
SPI write_buffer 01// only activate 1st chip select pin
SPI write_buffer fc// only activate the other chip select pins
Reading: see Basic OperationSPI purge_read_buffer
// optionally
SPI purge_write_buffer// optionally
SPI add dc 7f 8f8fb4 0123456789abcdef be SPI cs// get status of defined chip select pins
SPI cs_bar// same as above but with "active low" logic
SPI cs_set// set all available chip select pins to "active"
SPI transmit SPI cs_release// set all available chip select pins to "passive"
SPI cs_set 01// only activate 1st chip select pin to "active"
SPI transmit SPI cs_release// set all available chip select pins to "passive"
SPI cs_set fe// only activate the other chip select pins to "active"
SPI transmit SPI cs_release ee// set masked chip select pins to "passive", keep 5th "active"
SPI cs_release 10// set masked chip select pins to "passive", keep 5th "active"
SPI
SPI <list of data bytes|words|dwords|qwords>
SPI write <list of data bytes|words|dwords|qwords>
SPI w <list of data bytes|words|dwords|qwords>
DEBG
> 0 RECV SPI write OK
SPI add <list of data bytes|words|dwords|qwords>
SPI a <list of data bytes|words|dwords|qwords>
DEBG
> 0 RECV SPI add OK
SPI write_buffer [ <Chip Select Mask> ]
SPI wb [ <Chip Select Mask> ]
RECV SPI write_buffer
SPI transmit
SPI t
DEBG
> 0 RECV SPI transmit OK
SPI cs_set [ <Chip Select Mask> ]
SPI css [ <Chip Select Mask> ]
RECV SPI cs 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
cs
is called to show the current status SPI cs_release [ <Chip Select Mask> ]
SPI csr [ <Chip Select Mask> ]
RECV SPI cs 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
SPI read
SPI r
RECV SPI read <value>
<value>
SPI show_write_buffer [<Number of Bytes> [<Reverse Flag>]]
SPI sw [<Number of Bytes> [<Reverse Flag>]]
SPI sw
RECV SPI show_write_buffer elements: 0x5 (5)
RECV SPI show_write_buffer 10 00 10 21 42
SPI sw
RECV SPI show_write_buffer elements: 0x14 (20)
RECV SPI show_write_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_write_buffer (#2) 10 10 10 00 10 21 42 51 ...
RECV SPI show_write_buffer (#3) 25 01 10 10
<Number of Bytes>
set, <Number of Bytes>
≠0, SPI sw 3
RECV SPI show_write_buffer --
<Number of Bytes>
set, e.g. 4, SPI sw 4
RECV SPI show_write_buffer 10 00 10 21
<Number of Bytes>
set, e.g. 0xA, SPI sw a
RECV SPI show_write_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_write_buffer (#2) 10 10
<Number of Bytes>
set, e.g. 2, <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
) SPI sw 2 TRUE
RECV SPI show_write_buffer 10 10
<Number of Bytes>
set, e.g. 9, <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
) SPI sw 9 1
RECV SPI show_write_buffer (#1) 00 10 21 42 51 25 01 10 ...
RECV SPI show_write_buffer (#2) 10
8
(#i)
, starting from 1, is added in front
<Number of Bytes>
0
: all available
<Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
<Reverse Flag>
0,FALSE,OFF,LOW
: show <Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
<Number of Bytes>
elements from <number of elements> - <Number of Bytes>
until last added element
SPI show_read_buffer [<Number of Bytes> [<Reverse Flag>]]
SPI sr [<Number of Bytes> [<Reverse Flag>]]
SPI sr
RECV SPI show_read_buffer elements: 0x5 (5)
RECV SPI show_read_buffer 10 00 10 21 42
SPI sr
RECV SPI show_read_buffer elements: 0x14 (20)
RECV SPI show_read_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_read_buffer (#2) 10 10 10 00 10 21 42 51 ...
RECV SPI show_read_buffer (#3) 25 01 10 10
<Number of Bytes>
set, <Number of Bytes>
≠0, SPI sr 3
RECV SPI show_read_buffer --
<Number of Bytes>
set, e.g. 4, SPI sr 4
RECV SPI show_read_buffer 10 00 10 21
<Number of Bytes>
set, e.g. 0xA, SPI sr a
RECV SPI show_read_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_read_buffer (#2) 10 10
<Number of Bytes>
set, e.g. 2, <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
) SPI sr 2 TRUE
RECV SPI show_read_buffer 10 10
<Number of Bytes>
set, e.g. 9, <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
) SPI sr 9 1
RECV SPI show_read_buffer (#1) 00 10 21 42 51 25 01 10 ...
RECV SPI show_read_buffer (#2) 10
8
(#i)
, starting from 1, is added in front
<Number of Bytes>
0
: all available
<Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
<Reverse Flag>
0,FALSE,OFF,LOW
: show <Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
<Number of Bytes>
elements from <number of elements> - <Number of Bytes>
until last added element
SPI purge
SPI p
DEBG
> 0 RECV SPI purge OK
purge_write_buffer
and purge_read_buffer
SPI purge_write_buffer
SPI pw
DEBG
> 0 RECV SPI purge_write_buffer OK
SPI purge_read_buffer
SPI pr
DEBG
> 0 RECV SPI purge_read_buffer OK
SPI reset
DEBG
> 0 RECV SPI reset OK
SPI status
SPI s
SPI
RECV SPI status
RECV SPI cs 1:0 2:- 3:- 4:- 5:- 6:- 7:- 8:-
RECV SPI cs_bar 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
RECV SPI cs_pins 1:PORTB,0
RECV SPI cs_select_mask FF
RECV SPI control_bits 50
RECV SPI spi_enable TRUE
RECV SPI data_order 0
RECV SPI master TRUE
RECV SPI clock_polarity 0
RECV SPI clock_phase 0
RECV SPI speed 0
RECV SPI double_speed TRUE
RECV SPI speed_divider 4 (2500000Hz @ 10000000Hz)
RECV SPI transmit_byte_order 0 (MSB/big endian)
RECV SPI transmit_report FALSE
RECV SPI auto_purge_read_buffer TRUE
RECV SPI auto_purge_write_buffer FALSE
RECV SPI show_write_buffer elements: 0xd (13)
RECV SPI show_write_buffer (#1) AB BB AA BB CC EE FF 66 ...
RECV SPI show_write_buffer (#2) 54 12 45 54 58
RECV SPI show_read_buffer elements: 0 (0)
SPI cs [<Chip Select Mask>]
SPI cs
RECV SPI cs 1:0 2:- 3:- 4:- 5:- 6:- 7:- 8:-
0b01100001 = 0x71
SPI cs 71
RECV SPI cs 1:0 6:- 7:-
[<Chip Select Mask>]
<Pin States>
<Pin States>
: <Index>:<State>
<Index>
: 1 ... 8
<State>
: 1
: HIGH
0
: LOW
-
: undefined, channel not connected
SPI cs_bar [<Chip Select Mask>]
SPI csb [<Chip Select Mask>]
SPI csb
RECV SPI cs_bar 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
0b01100001 = 0x71
SPI csb 71
RECV SPI cs_bar 1:1 6:- 7:-
<Chip Select Mask>
<Pin States>
<Pin States>
: <Index>:<State>
<Index>
: 1 ... 8
<State>
: 1
: LOW
0
: HIGH
-
: undefined, channel not connected
SPI cs_pins [<CS Channel Index>]
SPI cs_pins
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
RECV SPI cs_pins 1:PORTB,0 2:PORTA,4 3:PORTG,4 7:PORTF,5
<CS Channel Index>
SPI cs_pins <CS Channel Index>
RECV SPI cs_pins <Index><PORTx>,<Pin>,<Status>
SPI cs_pins 1
RECV SPI cs_pins 1:PORTB,0,ON
<CS Channel Index>
1 ... 8
<List of active <Index>:<PORTx>,<Pin> CS Configurations>
<<Index>:<PORTx>,<Pin>,<Status> CS Configuration>
<Index>
1 ... 8
<PORTx>
PORTx
x
: A ... G
<Pin>
PORTx
0 ... 7
<Status>
ON
: active
OFF
: deactivated
SPI cs_select_mask [<Chip Select Mask>]
RECV SPI cs_select_mask <Value>
<Value>
is assigned to the configuration
<Value>
[0 ... FF]
SPI cs_add_pin <Symbolic Output Port Address> <Output Port Pin> [<Channel Select Index/Slot>]
SPI csap <Symbolic Output Port Address> <Output Port Pin> [<Channel Select Index/Slot>]
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
PORTX:Pin
combinations to act as channel select channels. Provided the chosen slots aren't used yet or the address set is already defined (see SPI cs_pins, SPI cs_remove_pin).<Channel Select Index/Slot>
: <Channel Select Index/Slot>
: <Symbolic Output Port Address>
PORTx
x
: A ... G
<Output Port Pin>
PORTx
0 ... 7
<Channel Select Index/Slot>
1 ... 8
SPI cs_remove_pin <Channel Select Index/Slot>
SPI csrp <Channel Select Index/Slot>
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
<Channel Select Index/Slot>
1 ... 8
SPI control_bits [<Extended SPI Control Register>]
SPI c [<Extended SPI Control Register>]
RECV SPI control_bits 50
RECV SPI spi_enable TRUE
RECV SPI data_order 0
RECV SPI master TRUE
RECV SPI clock_polarity 0
RECV SPI clock_phase 0
RECV SPI speed 0
RECV SPI double_speed TRUE
RECV SPI speed_divider 4 (2500000Hz @ 10000000Hz)
SPCR
and the SPI Status Register SPSR
en bloc. Therefore those two registers are combinded into one 16bit data word with SPCR
as LSB and SPSR
as MSB. Since SPSR
, despite its name, does have one control bit. <Extended SPI Control Register>
: <Extended SPI Control Register>
: <Extended SPI Control Register>
0 ... 1FF
SPI enable state: SPE
SPI spi_enable [<value>]
RECV SPI spi_enable ==SPI enable state: SPE==
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI Data Order: DORD
SPI data_order [<value>]
RECV SPI data_order
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI Master/Slave Select: MSTR
SPI master [<value>]
RECV SPI master
<value>
(0,) 1, ≠0, ON, (OFF), TRUE, (FALSE)
SPI Clock Polarity: CPOL
SPI clock_polarity [<value>]
RECV SPI clock_polarity
CPOL | Leading Edge | Trailing Edge |
---|---|---|
0 | Rising | Falling |
1 | Falling | Rising |
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI Clock Phase: CPHA
SPI clock_phase [<value>]
RECV SPI clock_phase
CPHA | Leading Edge | Trailing Edge |
---|---|---|
0 | Sample | Setup |
1 | Setup | Sample |
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI Clock Rate Select 1/0: SPR1/0
SPI speed [<value>]
RECV SPI speed
<value>
0 ... 3
speed | double speed | clock rate: SCK frequency |
---|---|---|
0 | OFF | fclkIO/4 |
1 | OFF | fclkIO/16 |
2 | OFF | fclkIO/64 |
3 | OFF | fclkIO/128 |
0 | ON | fclkIO/2 |
1 | ON | fclkIO/8 |
2 | ON | fclkIO/32 |
3 | ON | fclkIO/64 |
Clock Rate Divider
SPI speed_divider [<value>]
RECV SPI speed_divider
SCK frequency
<value>
2, 4, 8, 0x10, 0x20, 0x40, 0x80
SPI Double Speed Bit: SPI2X
SPI double_speed [<value>]
RECV SPI double_speed
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI transmit_byte_order [<value>]
RECV SPI transmit_byte_order
<value>
0, 1
<value> | transmit byte order |
---|---|
0 | MSB, big endian, FIFO |
1 | LSB, little endian, LIFO |
SPI transmit_report [<value>]
RECV SPI transmit_report
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI auto_purge_write_buffer [<value>]
RECV SPI auto_purge_write_buffer
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
SPI auto_purge_read_buffer [<value>]
RECV SPI auto_purge_read_buffer
<value>
0, 1, ≠0, ON, OFF, TRUE, FALSE
DACOUTx
, q.v. HadCon2/DAC) and are therefore shifted by -1 compared to the connector pin numeration from pin 1 to pin 8. The remaining pin 9 and 10 are ground.
(q.v. connector assignment)
DAC
: return all DACs value
DAC <CHANNEL>
: return current DAC value DAC: <CHANNEL> <VALUE_mV>
: set current DAC output to (approx.) wanted voltage RECV DAC <CHANNEL> <VALUE_mV> <VALUE_HEX> [undefined]
<CHANNEL>
: 0 - 7
<VALUE_mV>
: 0 - 3300 mV, undefined
→ -1
<VALUE_HEX>
: 0x00 - 0xFF, undefined
→ 0x100
undefined
: since there is no readback, values are undefined until a value is set, DAC
, you will get the above for each channel from 0 to 7 in a separate line.
Form:
RGWR <Register> <Value>
<Register> : the register address has to be written in hexadecimal<Value> : here has to be written the new register value in hexadecimal
<0|1> : used to execute write or read operation. This is the Least Significant Bit (LSB) from the I2C address byte.
<I2C address> : Here has to be written the hexadecimal value on the address byte, which is shifted to right with one bit. The reason for the right shift is because, the lsb bit ist already used in the first field, where the working operation is choosen. <data length> : data length <byte1 ... byte8> : data Example command:
send: I2C 0 70 1 08
receive: RECV I2C 0 70 01 08 -OK-
APFEL
command set
allows to talk to (several instances of) the APFEL ASIC.
It uses a subset of the the I/O-Ports of the ATMEL μController to facilitate the communication to the proprietary protocol (q.v.Decoder.pdf) of the asic, sending a 22bit sequence for command, value, and chipId.
( → Apfel protocol code sequences) CLK
DOUT
Side Select
DIN
GND
JDINOUT1/2, JADC
I/O port | A | C | F | |||
---|---|---|---|---|---|---|
Connector | JDINOUT1 | JDINOUT2 | JADC | |||
pins | DIN1 | 1 | DIN1 | 1 | DIN1 | 1 |
DOUT1 | 2 | DOUT1 | 2 | DOUT1 | 2 | |
CLK1 | 3 | CLK1 | 3 | CLK1 | 3 | |
SS1 | 4 | SS1 | 4 | SS1 | 4 | |
DIN2 | 5 | DIN2 | 5 | DIN2 | 5 | |
DOUT2 | 6 | DOUT2 | 6 | DOUT2 | 6 | |
CLK2 | 7 | CLK2 | 7 | CLK2 | 7 | |
SS2 | 8 | SS2 | 8 | SS2 | 8 |
task | command | individual arguments | common address arguments | comment |
---|---|---|---|---|
setDac | APFEL 9 <DAC value> <dac> <chipId> <pinSetId> <sideSelectId> <port> [<quiet>] answer (if not quiet): → readDac |
<DAC value> [ 0 ... 0x3FF ] <DAC> [ 1 ... 4 ] |
<chipId> [ 0 ... 7, 8 ... FE, FF] 0xFF: generic call to all available chip Ids <pinSetId> [ 1, 2 ] <sideSelectId> [ 0,1 ] <port> A,C,F <quiet> [0,1] |
writes DAC channel |
readDac | APFEL A <dac> <chipId> <pinSetId> <sideSelectId> <port> answers: RECV APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> ERRA APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> - read validity check failed, raw value: |
<DAC> [ 1 ... 4 ] |
reads single DAC channel | |
readAllDacs | APFEL A 0 <chipId> <pinSetId> <sideSelectId> <port> answers: RECV APFEL dac <port> <pinSetId> <sideSelectId> <chipId> 0 <DAC value1> <DAC value2> <DAC value3> <DAC value4> ERRA APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> - read validity check failed, raw value: |
*Not Yet Available* reads all DAC channels of an ch | ||
|
||||
autocalib | APFEL B <chipId> <pinSetId> <sideSelectId> <port> |
auto calibration | ||
|
||||
TP single | APFEL C <pulse height Pattern> <chipId> <pinSetId> <sideSelectId> <port> |
<pulse height Pattern> [ 2...3FF ] |
test pulse | |
TP reset | APFEL D <pulse height> <channel> <chipId> <pinSetId> <sideSelectId> <port> |
<pulse height Pattern> [ 1 ... F ] <channel> [ 1, 2 ] |
test pulse inkl. reset | |
TP trigger | APFEL 11 <on/off> <port> <pin> <trigger position> |
<on/off> [ 0,1 ] <port> [ A,B,C,D,E,F,G ] <pin> [1...8] <trigger after set (1) or after reset (2)> [1,2] |
<on/off> enables/disables <pin> on <port> to trigger right in the moment after a test pulse set or reset command sequence is sent | |
|
||||
setAmpl | APFEL E <channel> <chipId> <pinSetId> <sideSelectId> <port> |
<channel> [ 1, 2 ] |
setAmplification to high | |
resetAmpl | APFEL F <channel> <chipId> <pinSetId> <sideSelectId> <port> |
<channel> [ 1, 2 ] |
resetAmplification to low | |
|
||||
listId | APFEL 10 <all> <NChipIds> <pinSetId> <sideSelectId> <port> |
<all flag> [ 1...FF ] <number of chip Ids> [ 1...FF ] |
check <number of chip Ids> channels and list depending on the <all flag> all or only positive results | |
listId++ | APFEL 20 <all> <NChipIds> <minChipId> <pinSetId> <sideSelectId> <port> |
<all flag> [ 1...FF ] <number of chip Ids> [ 1...FF ] <min Chip Id> [ 1...FF ] |
check <number of chip Ids> channels and list depending on the <all flag> all or only positive results |
typical | best measured | "preHadCon2 Timings" ~× 8000 | ||
Clock Timing | T [µs] | 44.8 | 24.8 | 400,000 |
f [kHz] | 22.3 | 40.3 | 0.0027 | |
Function call overhead offset | [µs] | ~330 | ~300 | |
Task Timings | ||||
---|---|---|---|---|
Task | typical | best measured | ||
set DAC | [ms] | 2.4 | 1.4 | |
read DAC | [ms] | 2.7 | 1.6 | |
AutoCalibration | [ms] | 48.4 | 27 | |
AutoCalibration × 256 × 2 | [s] | 24.8 | 13.8 | |
TestPulseSequence | [ms] | 2.3 | 1.4 | |
TestPulse | [ms] | 4.7 | 2.7 | |
SetAmplitude | [ms] | 2.3 | 1.3 | |
ResetAmplitude | [ms] | 2.3 | 1.3 |
typical | "preHadCon2 Timings" ~× 104 | ||
Clock Timing | T [µs] | 40 | 400,000 |
f [kHz] | 25 kHz | 0.0027 | |
Function call overhead offset | [µs] | ~330 | |
Task Timings | |||
---|---|---|---|
Task | typical | ||
set DAC w/o readback | [ms] | 2 | |
read DAC | [ms] | 2.3 | |
set DAC w/ readback (estimate) | [ms] | 4.3 | |
AutoCalibration | [ms] | ~155 | |
AutoCalibration × 256 × 2 (estimate) | [s] | ~80 | |
TestPulseSequence | [ms] | 2 | |
complete TestPulse | [ms] | 4 | |
SetAmplitude | [ms] | 2 | |
ResetAmplitude | [ms] | 2 |
$CMND <command> $ADDRESS [<Argument(s)>]
command | address | arguments | comment | ||||
---|---|---|---|---|---|---|---|
"channel" | value(s) | ||||||
dac |
<portLetter> A,C,F, |
<pinSetId> [ 1, 2 ] |
<sideSelectId> [ 1, 2 ] |
<chipId> [ 0 ... 7, 8 ... FE, FF] 0xFF: generic call to all available chip Ids see command chipIdIgnoreMask for limiting the chipId range |
<dacId> [ 1 ... 4 ] < 4 , e.g. 0xA : all DACs get value vDAC1 |
[vDAC1[vDAC2[vDAC3[vDAC4]]]] [ 0 ... 0x3FF ] |
read/writes up to 4 DAC channels (if set with sign, incr/decr relatively) |
autoCalib |
auto calibration of the DAC channels | ||||||
testPulse |
<channelId> [ 1 ... 2 ] < 4 , e.g. 0xA : both channels |
height1 [height2] [ 0 ... 0xF ] |
initiate test pulse | ||||
ampl |
<channelId> [ 1 ... 2 ] < 4 , e.g. 0xA : both channels |
[ amplification1 [amplification2] ] [ 0,1, H,L ] 0,L : low amplification (× 16) 1,H : high amplification (× 32) |
get/set amplification mode | ||||
l/list |
lists all addresses of available ids |
<chipId>
to 0xFF
loops over all avaiable chip IDs
$CMND $command $ADDRESS <dacId>
$CMND $command $ADDRESS
$CMND $command <portId> <sideSelectId>
$CMND $command $ADDRESS <dacId ≤ 4 > <value>
$CMND $command $ADDRESS <dacId > 4> <value>
$CMND $command $ADDRESS <(dummy)> <valueDAC1> <valueDAC2> <valueDAC3> <valueDAC4>
RECV $CMND $command $ADDRESS <dacId> <value>
RECV $CMND $command $ADDRESS <dacId> <valueDAC1> <valueDAC2> <valueDAC3> <valueDAC4>