HadCon2 Multipurpose Controls Protocol Cmnd Apfel

Introduction

Api Basic Operation Principle

• HadCon 2 Multipurpose Controls Api Basic Operation

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General Operation

The APFEL command set allows to talk to (several instances of) the APFEL ASIC. It uses a subset of the the I/O-Ports of the ATMEL μController to facilitate the communication to the proprietary protocol (q.v.Decoder.pdf) of the asic, sending a 22bit sequence for command, value, and chipId. ( → Apfel protocol code sequences)
• Logically
  • Output:
    • CLK
      • quasi clock, only the level changes are important
    • DOUT
      • data out
    • Side Select
      • position
  • Input:
    • DIN
      • data in
  • GND
• Electrical:
  • 3.3 Volt
• Physically:
  • per default:
    • JDINOUT1/2, JADC
      • I/O ports:
        

        I/O port	A		C		F
        Connector	JDINOUT1		JDINOUT2		JADC
        pins	DIN1	1	DIN1	1	DIN1	1
        	DOUT1	2	DOUT1	2	DOUT1	2
        	CLK1	3	CLK1	3	CLK1	3
        	SS1	4	SS1	4	SS1	4
        	DIN2	5	DIN2	5	DIN2	5
        	DOUT2	6	DOUT2	6	DOUT2	6
        	CLK2	7	CLK2	7	CLK2	7
        	SS2	8	SS2	8	SS2	8

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Version 0

In the run of development an intermediate short command set has been implemented which is not so well descriptive as its future successor

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Commands

task	command	individual arguments	common address arguments	comment
setDac	APFEL 9 <DAC value> <dac> <chipId> <pinSetId> <sideSelectId> <port> [<quiet>] answer (if not quiet): → readDac	<DAC value> [ 0 ... 0x3FF ] <DAC> [ 1 ... 4 ]	<chipId> [ 0 ... 7, 8 ... FE, FF] 0xFF: generic call to all available chip Ids <pinSetId> [ 1, 2 ] <sideSelectId> [ 0,1 ] <port> A,C,F <quiet> [0,1]	writes DAC channel
readDac	APFEL A <dac> <chipId> <pinSetId> <sideSelectId> <port> answers: RECV APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> ERRA APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> - read validity check failed, raw value:	<DAC> [ 1 ... 4 ]		reads single DAC channel
readAllDacs	APFEL A 0  <chipId> <pinSetId> <sideSelectId> <port> answers: RECV APFEL dac <port> <pinSetId> <sideSelectId> <chipId> 0 <DAC value1> <DAC value2> <DAC value3> <DAC value4> ERRA APFEL dac <port> <pinSetId> <sideSelectId> <chipId> <dac> <DAC value> - read validity check failed, raw value:			*Not Yet Available* reads all DAC channels of an ch
autocalib	APFEL B <chipId> <pinSetId> <sideSelectId> <port>		auto calibration
TP single	APFEL C <pulse height Pattern> <chipId> <pinSetId> <sideSelectId> <port>	<pulse height Pattern> [ 2...3FF ]	test pulse
TP reset	APFEL D <pulse height> <channel> <chipId> <pinSetId> <sideSelectId> <port>	<pulse height Pattern> [ 1 ... F ] <channel> [ 1, 2 ]	test pulse inkl. reset
TP trigger	APFEL 11 <on/off> <port> <pin> <trigger position>	<on/off> [ 0,1 ] <port> [ A,B,C,D,E,F,G ] <pin> [1...8] <trigger after set (1) or after reset (2)> [1,2]		<on/off> enables/disables <pin> on <port> to trigger right in the moment after a test pulse set or reset command sequence is sent
setAmpl	APFEL E <channel> <chipId> <pinSetId> <sideSelectId> <port>	<channel> [ 1, 2 ]	setAmplification to high
resetAmpl	APFEL F <channel> <chipId> <pinSetId> <sideSelectId> <port>	<channel> [ 1, 2 ]	resetAmplification to low
listId	APFEL 10 <all> <NChipIds> <pinSetId> <sideSelectId> <port>	<all flag> [ 1...FF ] <number of chip Ids> [ 1...FF ]	check <number of chip Ids> channels and list depending on the <all flag> all or only positive results
listId++	APFEL 20 <all> <NChipIds> <minChipId> <pinSetId> <sideSelectId> <port>	<all flag> [ 1...FF ] <number of chip Ids> [ 1...FF ] <min Chip Id> [ 1...FF ]	check <number of chip Ids> channels and list depending on the <all flag> all or only positive results

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First Test Results (16 Jan 2015)

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First Test Results from 16 Jan 2015

• programm uses inline functions.

  		typical	best measured	"preHadCon2 Timings" ~× 8000
  Clock Timing	T [µs]	44.8	24.8	400,000
  	f [kHz]	22.3	40.3	0.0027
  Function call overhead offset	[µs]	~330	~300
  Task Timings
  Task		typical	best measured
  set DAC	[ms]	2.4	1.4
  read DAC	[ms]	2.7	1.6
  AutoCalibration	[ms]	48.4	27
  AutoCalibration × 256 × 2	[s]	24.8	13.8
  TestPulseSequence	[ms]	2.3	1.4
  TestPulse	[ms]	4.7	2.7
  SetAmplitude	[ms]	2.3	1.3
  ResetAmplitude	[ms]	2.3	1.3

Original Notes

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Logic Analyzer Results (14 Oct 2015)

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Logic Analyzer Results

Summary (10 Oct 2015)

		typical	"preHadCon2 Timings" ~× 104
Clock Timing	T [µs]	40	400,000
	f [kHz]	25 kHz	0.0027
Function call overhead offset	[µs]	~330
Task Timings
Task		typical
set DAC w/o readback	[ms]	2
read DAC	[ms]	2.3
set DAC w/ readback (estimate)	[ms]	4.3
AutoCalibration	[ms]	~155
AutoCalibration × 256 × 2 (estimate)	[s]	~80
TestPulseSequence	[ms]	2
complete TestPulse	[ms]	4
SetAmplitude	[ms]	2
ResetAmplitude	[ms]	2

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Details (port A - 10 Oct 2015)

set DAC	APFEL 9 3FF 3 1 1 1 A 1	%FOREACH{"item" in="setDac_APFEL_9_3FF_3_1_1_1_A_1_2015-10-14.png"}% %NEXT{"item"}%
readDAC	APFEL A 3 1 1 1 A	%FOREACH{"item" in="readDac_APFEL_A_3_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
autocalibration	APFEL B 1 1 1 A	%FOREACH{"item" in="autocalib_APFEL_B_1_1_1_A__2015-10-14.png"}% %NEXT{"item"}%
autocalibration (full)	APFEL B 1 1 1 A	%FOREACH{"item" in="autocalib_APFEL_B_1_1_1_A_(full)_2015-10-14.png"}% %NEXT{"item"}%
TP single	APFEL C 3 1 1 1 A	%FOREACH{"item" in="TP_single_APFEL_C_3_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
TP reset ch1	APFEL D 9 1 1 1 1 A	%FOREACH{"item" in="TP_reset_APFEL_D_9_1_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
TP reset ch2	APFEL D 9 2 1 1 1 A	%FOREACH{"item" in="TP_reset_APFEL_D_9_2_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
TP reset ch1 incl. Trig, Pos 1	APFEL D 9 1 1 1 1 A	%FOREACH{"item" in="TP_reset_inkl_Trig_Pos_1_APFEL_D_9_1_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
TP reset ch1 incl. Trig, Pos 2	APFEL D 9 1 1 1 1 A	%FOREACH{"item" in="TP_reset_inkl_Trig_Pos_2_APFEL_D_9_1_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%
set amplification	APFEL E 2 1 1 1 A	%FOREACH{"item" in="setAmplification_APFEL_E_2_1_1_1_A__2015-10-14.png"}% %NEXT{"item"}%
reset amplification	APFEL F 2 1 1 1 A	%FOREACH{"item" in="resetAmplification_APFEL_F_2_1_1_1_A_2015-10-14.png"}% %NEXT{"item"}%

Details (port F - 06 Nov 2015)

Trigger Level at 2.0V

set DAC	APFEL 9 3FF 3 1 1 1 F 1	%FOREACH{"item" in="setDac_APFEL_9_3FF_3_1_1_1_F_1_2015-11-06.png"}% %NEXT{"item"}%
readDAC	APFEL A 3 1 1 0 F	%FOREACH{"item" in="readDac_APFEL_A_3_1_1_0_F_2015-11-06.png"}% %NEXT{"item"}%
autocalibration	APFEL B 1 1 1 F	%FOREACH{"item" in="autocalib_APFEL_B_1_1_1_F_2015-11-06.png"}% %NEXT{"item"}%
TP single	APFEL C 3 1 1 0 F	%FOREACH{"item" in="TP_single_APFEL_C_3_1_1_0_F_2015-11-06.png"}% %NEXT{"item"}%
TP reset ch2	APFEL D 9 2 1 1 1 F	%FOREACH{"item" in="TP_reset_APFEL_D_9_2_1_1_1_F_2015-11-06.png"}% %NEXT{"item"}%
set amplification	APFEL E 2 1 1 0 F	%FOREACH{"item" in="setAmplification_APFEL_E_2_1_1_0_F_2015-11-06.png"}% %NEXT{"item"}%
reset amplification	APFEL F 2 1 1 1 F	%FOREACH{"item" in="resetAmplification_APFEL_F_2_1_1_1_F_2015-11-06.png"}% %NEXT{"item"}%

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Version 1

not yet implemented, but you may have a look ...
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%FOREACH{"ADDRESS" in="<portLetter> <portIndex> <sideSelectionId> <chipId>"}% %FOREACH{"CMND" in="APFEL"}%

Overview

overall main command structure:
$CMND <command> $ADDRESS  [<Argument(s)>]

command	address			arguments		comment
				"channel"	value(s)
dac	<portLetter> A,C,F,	<pinSetId> [ 1, 2 ]	<sideSelectId> [ 1, 2 ]	<chipId> [ 0 ... 7, 8 ... FE, FF] 0xFF: generic call to all available chip Ids see command chipIdIgnoreMask for limiting the chipId range	<dacId> [ 1 ... 4 ] < 4, e.g. 0xA: all DACs get value vDAC1	[vDAC1[vDAC2[vDAC3[vDAC4]]]] [ 0 ... 0x3FF ]	read/writes up to 4 DAC channels (if set with sign, incr/decr relatively)
autoCalib						auto calibration of the DAC channels
testPulse				<channelId> [ 1 ... 2 ] < 4, e.g. 0xA: both channels	height1 [height2] [ 0 ... 0xF ]	initiate test pulse
ampl				<channelId> [ 1 ... 2 ] < 4, e.g. 0xA: both channels	[ amplification1 [amplification2] ] [ 0,1, H,L ] 0,L: low amplification (× 16) 1,H: high amplification (× 32)	get/set amplification mode
l/list						lists all addresses of available ids

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%FOREACH{"command" in="dac"}% %FOREACH{"alternative" in="d"}%

$CMND $alternative/$command

Task

Format

• NOTE: setting <chipId> to 0xFF loops over all avaiable chip IDs
• read
  • single DAC at port/pos/chipId:
    $CMND $command $ADDRESS <dacId>
    
  • all 4 DACs at port/pos/chipId:
    $CMND $command $ADDRESS
    
  • all 4 DACs of all available chipIds at port/pos:
    $CMND $command <portId> <sideSelectId>
    
• write
  • single DAC at port/pos/chipIds:
    $CMND $command $ADDRESS <dacId ≤ 4 > <value>
    
  • all 4 DACs at port/pos/chipId with same value:
    $CMND $command $ADDRESS <dacId > 4> <value>
    
  • all 4 DACs at port/pos/chipId with individual values:
    $CMND $command $ADDRESS <(dummy)> <valueDAC1> <valueDAC2> <valueDAC3> <valueDAC4>
    

Response

• single dac channel access
  
  RECV $CMND $command $ADDRESS <dacId> <value>
• any other plots per found chip
  
  RECV $CMND $command $ADDRESS <dacId> <valueDAC1> <valueDAC2> <valueDAC3> <valueDAC4>

Description


read or write values from/to DAC channel(s) (if set with sign, incr/decr relatively)

Arguments

• <portId>
• <posId>
• <chipId>
• <dacId>
• <value>

Comments

• see cim/chipIdIgnoreMask

--- %NEXT{"alternative"}%%NEXT{"command"}%

%FOREACH{"command" in="autocalib"}% %FOREACH{"alternative" in="a"}%

$CMND $alternative/$command

Task

Format

Response

Description

Comments

--- %NEXT{"alternative"}%%NEXT{"command"}%

%FOREACH{"command" in="testPulse"}% %FOREACH{"alternative" in="t"}%

$CMND $alternative/$command

Task

Format

Response

Description

Comments

--- %NEXT{"alternative"}%%NEXT{"command"}%

%FOREACH{"command" in="ampl"}%

$CMND $command

Task

Format

Response

Description

Comments

--- %NEXT{"command"}%

%FOREACH{"command" in="list"}% %FOREACH{"alternative" in="l"}%

$CMND $alternative/$command

Task

Format

Response

Description

Comments

--- %NEXT{"alternative"}%%NEXT{"command"}%

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%NEXT{"CMND"}% %NEXT{"ADDRESS"}%

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• apfel.tar.gz: Shell scripts used for testing the basic functionality before implementation
• Decoder.pdf: Apfel decode version 1_4