Time Protocols in NUSTAR
Time Protocols refer to various ways to synchronise and distribute clock and timestamp information to the many DAQ systems within NUSTAR.
The gold standard and ideal solution is White Rabbit, which also provides timing to the GSI and FAIR accelerators.
More information on White Rabbit in this context is available at:
https://wiki.gsi.de/TOS/Timing/WebHome
For DAQ use, White Rabbit specifies a 125 MHz clock with "low ns" timestamp accuracy (1 ns resolution) and "low ps" jitter of the clock edge.
I.e, a system using a White Rabbit-derived clock has a "low ps" absolute time, see pages 78-81:
https://www.gsi.de/fileadmin/EE/MBS/mbs_overview.pdfNUSTAR DAQs can connect to the White Rabbit network at GSI with approved receivers: VETAR (VME), PEXARIA (PCIe) and WR-EXPLODER (Standalone).
For DAQs that cannot use an approved receiver directly, various other protocols are used to transmit the WR (potentially at reduced quality). A summary table is shown below.
Additional detail is provided in the attached slides:
time_protocols.odp time_protocols.pdf
| Protocol |
DC Bal |
PLL |
Medium |
Transmit |
Receive |
Encoding |
Record |
Rate |
WRTCLK |
Future |
| White Rabbit |
Y |
Y |
Single-Mode Fiber |
WR Xmitter |
WR Receiver |
Ethernet 8b10b |
|
1.25 GHz |
|
Reference time |
| Ratatime |
Y |
N |
Any* |
FPGA |
FPGA |
Self-aligning Pattern |
|
1-10 MHz |
Out |
Deprecate |
| Heimtime |
N |
N |
Any* |
FPGA |
PC Complex |
Periodic+Data |
Y |
200-400 Hz Varying |
Out |
Deprecate |
| Rataclock PLL |
Y |
Y |
Any* |
FPGA |
FPGA |
PWM Clock |
|
> 5 MHz |
Out |
|
| Rataclock Slow |
Y |
Y? |
Any* |
FPGA WR-LM32 |
FPGA |
PWM Clock |
|
1-10 MHz |
Out |
|
| Heimtime II |
|
|
Any* |
FPGA WR-LM32 |
PC FPGA |
Periodic+Data |
Y |
10 Hz-100 kHz |
|
FPGA Version |
| Clock + "Schakel" |
Y+N |
Y |
2x LVDS |
FPGA |
FPGA |
Clock + Time Data |
|
Clock: 200 MHz Timestamp: 50 MHz@100 kHz |
In |
|
| Clock + Reset |
N |
Y |
2x Any* |
(FPGA) |
(FPGA) |
Clock Reset |
|
|
|
Not Timing DO NOT USE |
Any* = Arbitrary digital I/O of suitable speed: NIM, ECL, LVDS, etc
DC Balanced: Constant DC average (0 and 1 equal over a long time)
PLL: Clock recovery via PLL
Transmit: Code to transmit, WM-LM32 is softcore in WR modules
Receive: Code for receiver
Record: Can be recorded in DAQ channel (low rate)
Rate: Approx. signal rate/required bandwidth
WRTCLK: Handled by WRTCLK Gateware
Ratatime description (see "Serial timestamp distribution"):
https://fy.chalmers.se/~f96hajo/trloii/vulom4_trlo/description.html
(Old) Heimtime description: (see "Heimtime (speaking clock) sender"):
https://fy.chalmers.se/~f96hajo/trloii/vulom4_trlo/description.html
Rataclock description:
https://fy.chalmers.se/~f96hajo/rataser/
--
NicolasHubbard - 2026-01-16