ACU Firmware Change Log

Refer to ACUFirmwareReleaseNotes for further release information and possibly known issues.

40 x Digital Interlock Module

FG660.14x

7.1.1 (28.02.2020)
  • FSP055 added for water-flow monitor visualization

7.1.0 (10.04.2019)
  • Added Digital interlock filter.
  • Fixed Interlock mask: only 40 interlocks and not 63 were really maskable.
  • Updated ACU_CommandDecoder module

7.0.2 (28.09.2018)
  • It possible to update the firmware via USB stick
7.0.1 (13.09.2018)
  • Fixed ACU_InputFilter.vhd: the main counter has to be set to zero if its value is greater or equal to the delay setting
  • ACU_WatreFlowAndICM_TDM.vhd: the period measure can be triggered from the pulse rising or falling edge. A ddedicated geneic selects the trigger mode

7.0.0 (31.03.2017)
  • First release of the 7 Series

ADC II

FG660.04x

7.1.1 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module
7.1.0 (13.11.2019)
  • Included correction factor(from MFU)

ADC DAC IO Module

FG660.18x

7.0.0 (31.03.2017)
  • First release of the 7 Series

ADC DAC IO Modul II

FG660.46x
7.2.1 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.2.0 (20.03.2019)
  • Added Digital interlock filter.
  • - Added PI controller (for Raul's PC)

7.1.1 (02.11.2018)
  • It possible to update the firmware via USB stick

7.1.0 (06.07.2018)
  • Re-arranged the code compliant with the FUG requirements.
  • The module can manage up to 3 USIs connections at the same time without any HW selection:
    • 2 USIs on the backplane
    • 1 USI on the front plane
      • USI_Slave_1 → full equipped
      • USI_Slave_2 → HighSpeed data transfer
    • 1 USI on the front plane

7.0.0 (12.06.2018)
  • Changed class to 26 for the USI slave 2 and 3 "dummy"
  • Generated FW version 7_0_0 instead of the "TestVersion"

Analog Interlock Module (AIM)

FG660.56x

7.1.1 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.1.0 (25.03.2019)
  • Added Digital interlock filter.

Interlock Control Module III (ICM)

 FG660.05x

7.3.2 (20.03.2020)
  • MPS Ready
  • Updated ACU_AlteraRemoteUpdate module
  • FSP045 ist nun 7 Bytes tief (anstelle 6 Bytes) wegen neuem Adressbreich für zukünftige FPGA Generationen
  • FSP055 fuer Wasserwaechter-Anzeige eingebaut
  • Das Aktivität des 2ten USI wird nun auch mittels LEDs angezeigt.

7.3.1 (10.04.2019)
  • Added three state buffer in combination with an open drain to the USI_SLAVE_LOCAL_TRIPLINE_OK output pin in order to properly manage the HW tripline propagation.

7.3.0 (21.01.2019)
  • Added second USI Slave "dummy" used to carry a generic 20 bits value from the MFU to the ICM.
    This feature was necessary to avoid to implemet a third PI controller in the MFU FW and use the ones already inside the ICM FW.
7.2.1 (13.09.2018)
  • Fixed ACU_InputFilter.vhd: the main counter has to be set to zero if its value is greater or equal to the delay setting
  • ACU_WatreFlowAndICM_TDM.vhd: the period measure can be triggered from the pulse rising or falling edge. A dedicated generic selects the trigger mode

7.2.0 (25.07.2018)
  • added electrical interlock digital filter

7.0.0 (31.03.2017)
  • First release of the 7 Series

MFU LE (Legacy)

FG660.012...FG660.017

7.0.2 (09.03.2018)
  • Fixed MFU_SwitchingOperations module
  • Added new ADC_732x_Control strategy
  • Set to all zeros the Intr_Enable SCU_Bus_Slave generic
  • Changed MFU FSP97 Reset default from "00" to "11"
  • Changed MFU Nios Input from intScopePreTriggerOffset[8..1]to FSP116_intScopeTriggerOffset[8..1]

7.0.0 (31.03.2017)
  • First release of the 7 Series

MFU SE (Second Edition)

FG660.018, FG660.019

7.5.1 (16.06.2020)
  • Updated ACU_AlteraRemoteUpdate module
  • Replaced Input FSPs with ACU_InputFSP_RAM_MFU module.
  • Changed Mux16To10 module: The High Speed USIs (Incoming and outgoing) are set to zero in case there is no module defined in PCA.
  • Added updated quadratic function generators (they have the sysclk used as clock enable signal because sysclk in MFU boards privious 19 serie is not connected to a pin clock)
  • Added DAQ module: the provided DAQ file doesn't contain the sysclk functionality like in the function generators, so it is supplied with 100MHz cock signal.

7.5.0 (12.11.2019)
  • DAC driver moved to TFT FPGA
  • Correction factor moved to ADC FPGA
  • Re arranged the MUX input signal
  • Reduce to 4 input the internal scope
  • Removed FSP066
  • Mux16To10 reduced resources implemented
  • Added new NIOS core

7.4.0 (06.02.2019)
  • Added Actual value to the High speed data outgoing mux (for Raul PCs)
  • Added SlopeLimiterC1 output as possible input to the Adder C1 (for Raul PCs)
  • Removed Linear function generators.
  • MDS generic "wModuleSubClass" from 0 → 1
  • Instance update "inst_ACU32BitMux_11to1" → "inst_ACU33BitMux_11to1"
7.3.2 (31.10.2018)
  • Added new slope limiter module: when the controller enable signal is low, the SL output follows the ActuelValue signal.
    As soon as controller enable signal rises up, the SL output starts to reach the configured SetVAlue, starting not anymore from zero, but from the last ActualValue sample
  • Generated ACU_SlopeLimiter V2.4:
    The SetValue starting point is always the Actual value sampled when the slope limiter is turned on(DR 29/10/2018)

7.3.1 (04.05.2018)
  • ACU_2_SCUB_RegisterCompatibilityInterface Update auf V1.2

7.3.0 (27.04.2018)
  • removed GLAD current comparator
  • introduced the PI coefficients selector in the PI controller
  • added new outgoing HS data format for GLAD (ActVal1 &ActVal2)
  • added new ACU_SlopeLimiter version
  • added new modular comparator version (data input length defined via generic)

7.0.2 (09.03.18)
  • Fixed MFU_SwitchingOperations module
  • Added new ADC_732x_Control strategy
  • Set to all zeros the Intr_Enable SCU_Bus_Slave generic
  • Changed MFU FSP97 Reset default from "00" to "11"
  • Changed MFU Nios Input from intScopePreTriggerOffset[8..1]to FSP116_intScopeTriggerOffset[8..1]

7.0.0 (31.03.2017)
  • First release of the 7 Series

Parallel Feeder

Same hardware as Static Converter III (FG660.09x) but completely different functionallity.

7.2.1 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.2.0 (10.04.2019)
  • Added Digital interlock filter.
  • Updated ACU_CommandDecoder module
  • Added three state buffer in combination with an open drain to the USI_SLAVE_LOCAL_TRIPLINE_OK output pin in order to properly manage the HW tripline propagation.

7.1.3 (28.09.2018)
  • It possible to update the firmware via USB stick
7.1.2 (19.09.2018)
  • Fixed Board serial number in input to the FSP0
  • Added onewire modules to read the boards serial number

7.1.1 (20.06.2018)
  • Changed baud rate to 20Mbaud
  • Updated MDS modules

7.1.0 (11.06.2018)
  • Added new ACU_ModularComparator version
  • Added "generic" USI Slave 3 MSD description

Semiconductor Monitoring Module

FG660.073x

7.0.0 (23.10.2018)
  • First release of the 7 Series

SR Injection Septa

Same hardware as Static Converter III (FG660.09x) but completely different functionallity.

7.1.2 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.1.1 (27.09.2019)
  • Added changes to have full dinamic output firing signals
7.1.0(04.09.2019)
  • Added interlocks from x28 extension module.
  • ZFC_CmdGen: the thyristor firing signal is driven by the set value coming from the main power converter only when it is on.
  • Moved the DCCT correction factor from the MFU to the ADC
  • Adapted ADC command decoder in order to be compliant with the MPS bit
  • Adapted ICM command decoder in order to be compliant with the MPS bit
  • Moved DAC driver from MFU to TFT
  • Adapted SR command decoder in order to be compliant with the MPS bit
  • Adapted TS1MU1 command decoder in order to be compliant with the MPS bit
  • Adapted ZFC command decoder in order to be compliant with the MPS bit 7.0.0 (25.08.2019)
  • First release of the 7 Series

Static Converter III

FG660.09x

7.3.2 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.3.1 (13.11.2019)
  • Updated ACU_CommandDecoder module
  • Updated ACU_mUSIC_Shell module
  • Updated USI Module
  • Updated USI_MergerDistribuitor
  • MPS ready

7.3.0 (10.04.2019)
  • Added Digital interlock filter.
  • Updated ACU_CommandDecoder module
  • Added three state buffer in combination with an open drain to the USI_SLAVE_LOCAL_TRIPLINE_OK output pin in order to properly manage the HW tripline propagation.

7.2.1 (28.09.2018)
  • It possible to update the firmware via USB stick
7.2.0 (11.10.2018)

7.1.2 (19.09.2018)
  • Fixed Board serial number in input to the FSP0

7.1.1 (20.06.2018)
  • Changed baud rate to 20Mbaud
  • Updated MDS and OneWire _Device.vhd modules

7.1.0 (11.06.2018)
  • Added new ACU_ModularComparator version
  • Added "generic" USI Slave 2 MSD description
  • Added the current comparator removed from the MFU FW

TS1MU1

Same hardware as Static Converter III (FG660.09x) but completely different functionallity.

7.2.2 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.2.1 (13.11.2019)
  • MPS Ready

7.2.0 (10.04.2019)
  • Added Digital interlock filter.
  • Updated ACU_CommandDecoder module
  • Added three state buffer in combination with an open drain to the USI_SLAVE_LOCAL_TRIPLINE_OK output pin in order to properly manage the HW tripline propagation.

7.1.4 (28.09.2018)
  • It possible to update the firmware via USB stick
7.1.3 (19.09.2018)
  • Fixed Board serial number in input to the FSP0

7.1.2 (20.06.2018)
  • SlopeLimiter Controller 1 war nicht am Differenzbilder angeschlossen

7.1.1 (15.06.2018)
  • max. Baudrate von 115k auf 20M geaendert

7.1.0 (11.06.2018)
  • Added new ACU_ModularComparator version
  • Added new ACU_TS1MU1SetValue version
  • Added "generic" USI Slave 3 MSD description

MFU TFT Front Panel

FG660.02x

7.1.1 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.1.0 (13.11.2019)
  • Added DAC driver and gain/offset module (from MFU)

7.0.1 (28.09.2018)
  • RemoteUpdate Problem für .rbf Dateien via USB Stick behoben.
7.0.0 (31.03.2017)
  • First release of the 7 Series

Water Interlock Control Module III (WICMII)

FG660.15x

7.0.2 (18.02.2020)
  • Updated ACU_AlteraRemoteUpdate module (Application Image)
  • Added ACU_InputFSP_RAM module
  • Fixed Temperature (Power,FPGA and Environment) order.

7.0.1 (13.09.2018)
  • Fixed ACU_InputFilter.vhd: the main counter has to be set to zero if its value is greater or equal to the delay setting
  • ACU_WatreFlowAndICM_TDM.vhd: the period measure can be triggered from the pulse rising or falling edge. A ddedicated geneic selects the trigger mode

Zero Field Control (ZFC)

Same hardware as ADC DAC IO Ver. II (FG660.46x) but completely different functionallity.

7.2.3 (19.12.2019)
  • Updated ACU_AlteraRemoteUpdate module

7.2.2 (13.11.2019)
  • Changed the tyristor firing signal generation strategy: the tyristor firing signal follows the setvalue comparator output only when the main power converter is on, otherwise it is set to zero.

7.2.1 (01.07.2019)
  • The output enable not delayed is used as PI controller/ PWM generator enable signal.

7.2.0 (10.04.2019)
  • Added Digital interlock filter.

7.1.2 (25.06.2018) 7.1.0 (11.06.2018)
  • Added new ACU_ModularComparator version
  • Added "generic" USI Slave 2 MSD description

7.0.0 (11.01.18)
  • First release of the 7 Series

-- DerekSchupp - 2019-02-06
Topic revision: r13 - 2020-09-02, DerekSchupp
 
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