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Meeting minutes:
Kick-off meeting - EPICS for Xilinx FPGA based embedded Systems



Realization of EPICS on Xilinx FPGA based embedded Systems

CBM is interested in having EPICS available on Xilinx Virtex4/5 (and potentially also Spartan1) based front-end DAQ electronic components to be able to remotely
  • modify/initiate setup configurations (of locally connected devices/infrastructure)
  • control running applications
  • Access to the component is TCP/IP based
    • either directly via an Ethernet controller or
    • piggyback on the DAQ data stream
      • Since EPICS also uses UDP, this protocol has to be supported in this piggyback mode
  • A Linux flavour distribution (PPC appreciated) is provided, which should allow the port of EPICS to the target architecture. It is based on the KIP's (Heidelberg) FPGA Environment Platform for the (soft) cores
    • PPC (for Virtex-4 FX based boards, hard core)
    • MicroBlaze (a very compact, non-mmu 32 bit soft core processor)
    • Leon (a SPARC V8 soft core, see Leon3 from Gaisler Research)
  • WFJM will contact KIP for supporting PZ with the Environment Tools
proposed Hardware Platforms:
  • ml403: Xilinx' Evaluation Board for Virtex4,
    • already available at EE/KS, bought by WFJM
  • SysCore V1 board, a generic prototype for CBM front-end and DCS components. Details on SysCore project page
    • currently being produced at GSI
  • read-out controler board (ROC) of the CBM n-XYTER read-out chain
proposed Software Features:
  • simple Soft IOC
  • Soft IOC able to control other processes running in parallel to EPICS
  • access to external (external to the FPGA, but still on the board) devices,
    • probably using simple register access mechanisms
    • maybe extended to higher protocols
    • realization:
      • device support modules / driver
  • complete configuration of the setup of the n-xyter board via EPICS
to be detailed:
  • available Test-configurations:
    • SysCore
    • n-XYTER read-out chain, consisting of FEB and ROC. The EPICS interface has to control, directly or via software processes running on the local processor, the components on the FEB, most notably the n-XYTER chips, and the DAQ data flow environment on the ROC, which will have hardware (e.g. in FPGA) and software components.
    • ...
person(s) in charge
  • development / project responsibility: Peter Zumbruch
  • additional EPICS support: Burkhard Kolb
  • FPGA - Linux Platform Environment: KIP Heidelberg (Udo Kebschull et al. (probably: Norbert Abel1))


next meeting

  • June, 27th, 2007, 14-15 GSI Kantine
  • topic: project decision

-- PeterZumbruch - 18 June 2007

Topic revision: r12 - 2007-06-18, PeterZumbruch - This page was cached on 2024-07-18 - 10:36.

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