Implement an USI interface in your own FPGA project.

If you plan to develop your own module for an ACU connection, it is necessary to do this via USI.


See "Understanding USI" to get started.


You can find examples of the necessary hardware connection here.


For the implementation of a USI in an FPGA project, download the following example.
  • mUSIc_Example_080922 - Released -
    Updates Date Note
    documents updated
    missing file added: ACU_USI/vhdl/UART_behavioural_model.vhd
    u3 22.07.22 mUSIc_Shell.bsf/mUSIc-Shell.bdf updated
    u4 08.09.22 mUSIc_Shell.vhd/ConnectionBetweenMasterAndModule updated
This is a project for an Intel (formerly Altera) FPGA.
To open the project you need QuartusII; available free of charge in the web edition from the manufacturer's website.
Since the project was created entirely in VHDL, it can be ported to FPGAs from other manufacturers without any problems.

-- DerekSchupp - 2021-12-01
Topic revision: r6 - 2022-09-08, DerekSchupp
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