Implement an USI interface in your own FPGA project.

If you plan to develop your own module for an ACU connection, it is necessary to do this via USI.

Documents

See "Understanding USI" to get started.

Hardware

You can find examples of the necessary hardware connection here.

Firmware

For the implementation of a USI in an FPGA project, download the following example.
  • mUSIc_Example_080922 - Released - u4.zip
    Updates Date Note
    u1
    22.06.22
    documents updated
    u2
    14.07.22
    missing file added: ACU_USI/vhdl/UART_behavioural_model.vhd
    u3 22.07.22 mUSIc_Shell.bsf/mUSIc-Shell.bdf updated
    u4 08.09.22 mUSIc_Shell.vhd/ConnectionBetweenMasterAndModule updated
This is a project for an Intel (formerly Altera) FPGA.
To open the project you need QuartusII; available free of charge in the web edition from the manufacturer's website.
Since the project was created entirely in VHDL, it can be ported to FPGAs from other manufacturers without any problems.

-- DerekSchupp - 2021-12-01
Topic revision: r6 - 2022-09-08, DerekSchupp - This page was cached on 2022-12-04 - 02:08.

This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding GSI Wiki? Send feedback | Legal notice | Privacy Policy (german)