Children of TimingSystemDocumentsReportsAndMeasurements in TOS/Timing Web
Results from TOS/Timing web retrieved at 06:57 (Local)
DBBasedAnalysisOfTimingMessages
Main.MathiasKreider 01 Dec 2021 Using snoop outputs for analysis of what's going on in the accelerator Purpose * One Thing * Lorem ipsum ... ...
NEW - 2021-12-02 - 10:33 by mkreider
ExcessivePtpAndLldpTraffic
WR PTP synchronization of WRS under excessive PTP and LLDP traffic 1. Introduction The White Rabbit (WR) technique is specially developed to provide sub nanose...
NEW - 2022-05-27 - 15:34 by eochirs
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 2017-11-30 - 15:24 by mreese
SnoopAnalysisBoosterTest1
Booster Test November 2021 Introduction The so called 'Booster Mode' shall be used to accumulate beam from multiple SIS18 injections into SIS100 at a rate of abo...
r10 - 2021-12-22 - 10:26 by dbeck
TimingSystemDocumentRep20180131
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
r9 - 2019-01-15 - 13:46 by dbeck
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
r6 - 2018-09-27 - 16:40 by dbeck
TimingSystemDocumentRep20190221
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
r3 - 2019-02-21 - 11:46 by dbeck
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
r8 - 2019-09-20 - 14:42 by dbeck
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
r8 - 2019-12-27 - 12:46 by dbeck
TimingSystemDocumentRep20210218
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
NEW - 2021-02-18 - 10:25 by dbeck
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
r6 - 2018-01-30 - 10:55 by dbeck
TimingSystemDocumentsRep20211222
Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...
r6 - 2022-01-13 - 10:04 by dbeck
TimingSystemIrradtionHHD
Irradiation of Fibres at HHD Cave (SIS18 beam dump) Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be poss...
r3 - 2024-04-22 - 07:44 by dbeck
TimingSystemIrradtionSIS18
Irradiation of Fibres at SIS18 Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be possible, that fibres to ...
r9 - 2024-04-22 - 07:43 by dbeck
Number of topics: 14
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