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HadCon Multipurpose Controls Protocol Cmnd Apfel Details Of The Protocol

Introduction

The communication with the APFEL chip on the signal level

Main

Bits

Bits are represented by a sequence of 5 states of the pins DOUT and CLK

High

  1. DOUT low + CLK low
  2. DOUT high + CLK low
  3. DOUT high + CLK high
  4. DOUT low + CLK high
  5. DOUT low + CLK low

Low

  1. DOUT low + CLK low
  2. DOUT high + CLK low
  3. DOUT high + CLK high
  4. DOUT low + CLK high
  5. DOUT low + CLK low

Measurements

Bits.png
  • ~25μs per bit
    • → max 40kBit/s
    • or 5μs per state change
  • + 10μs
    • → max 28kBit/s

execution times of the api

  • using artificial markers before and after the parser give
    • a minimum of ~37μs per call
    • typical values of ~1.2ms (w/o any output)
    • typical values of ~12 ms (with output)
    • typical values of ~15 ms (with error output)
    • maximum 125ms (autocalibration)

commands

    The full command sequence consists of:
    1. stream header
    2. the actual command sequence
    3. command specific sequences

    stream header

      This actual command sequence is prefixed by a stream header consisting of
      1. clear data input, i.e.
        1. for each command sequence bit (22)
          • write 1 clock sequence:
            • equivalent to: write 1 low bit
          • each 8 bit with 2 additional sequences of
            • DOUT low + CLK low
        2. followed by 10 sequences of the same
          • DOUT low + CLK low
        • ⇒ summed up roughly ~620μs
        • ⇒ measured ~620μs ~760-840μs
      2. the set
        • DOUT low + CLK low
          • to allow side selection bit to change before any action
      3. the sequence
        1. DOUT low + CLK low
        2. DOUT high + CLK low
        3. DOUT high + CLK high
        4. DOUT high + CLK low ⇐ this is the only difference to a low bit sequence
        5. DOUT low + CLK low

    command sequence

      The bare command set of the APFEL protocol is a big-endian sequence of 22 bits:
      1. 4 command bits
      2. 10 value bits
      3. 8 chip id bits

    command specific sequences

      setDac
        1. 3 clock cycles
          • equivalent to 3 low bit sequences
        2. (optional) the complete readDac sequence

      readDac
        1. read bit sequence for
          1. 2 leading bits
          2. 10 value bits
          3. 3 trailing bits
        2. followed by 3 clock cycles
          • equiv. to 3 low bit
        read bit sequence
          1. DOUT low + CLK low
          2. Initial bit and the rest
            1. Initial bit
              • since the APFEL needs first the falling clock endge to activate the output pad, the initial bit is read differently
              1. CLK high
              2. CLK low
              3. read PIN
            2. Remaining bit
              1. CLK high
              2. read PIN
              3. CLK low

      auto calibration
        1. 4 × 1024 = 4096 clock cycles

      test pulse - sequence
        1. 3 clock cycles

      set/reset amplification
        1. 3 clock cycles

    Example

      Example: command E: CommandSequence.png


-- PeterZumbruch - 30 Mar 2015
-- PeterZumbruch - 2015-03-30
Topic attachments
I Attachment Action Size Date Who Comment
Bits.pngpng Bits.png manage 5.6 K 2015-03-30 - 09:55 PeterZumbruch Bit timing
CommandSequence.pngpng CommandSequence.png manage 5.6 K 2015-03-30 - 14:08 PeterZumbruch Apfel command sequence for Command E
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Topic revision: r3 - 2015-03-30, PeterZumbruch
 
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