Project: GRISU

Abstract:

Radiation damages to electronic components are an important issue for future FAIR experiments. One of the preferred technology for ASIC developments at GSI is the 180nm UMC CMOS process. In this regard the ASIC design group of the GSI Experiment Electronic department has been launched a research project in 2007, including the development of an ASIC called GRISU. The main goal is the characterisation of Single Event Effects (SEE) as well as Total Ionising Dose (TID) effects on the 180nm UMC process.

Documents:

coming soon...

Papers:

Talks:

Internal EE group meeting talks:

GSI IT/EE palaver:

CBM meeting talks:

Other meetings / talks:

Timetable of project:

  • Feb 2007: Submission of GRISU test ASIC
  • Jun 2007: First tests of GRISU chip
  • Oct 2007: First test beam at X6 (functional test with C-12)
  • Jan 2008: Submission of GRISU2 test ASIC
  • Feb 2008: Test beam with Ni-58 at X6 (11.4 MeV/AMU)
  • Apr 2008: Test beam with C-12 at X6 (11.4 MeV/AMU)
  • Mai 2008: Testing of GRISU2 chip
  • Jul 2008: Test beam with Xe-132 at X6 (11.4 MeV/AMU)
  • Jul 2008: Test beam with C-12 at X6 (11.4 MeV/AMU)
  • Jul 2008: TID test with X-rays at FZ Karlsruhe (60 keV X-rays)
  • Sep 2008: Annealing test
  • Jan 2009: Test beam with Ar-40 at X6 (11.4 MeV/AMU)
  • Mar 2009: Test beam with Ru-96 at X6 (11.4 MeV/AMU)
  • Mai 2009: First microbeam test with Xe-132 at X0 (4.8 MeV/AMU) (Electrical test, software test, low statistic)
  • Feb 2010: Heavy Ion Microprobe test with Au-196 at X0 (data for statistic)

plans:

-- SvenLoechner - 14 May 2012
Topic revision: r15 - 2012-05-14, SvenLoechner
 
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