HadCon Multipurpose Controls Protocol Cmnd Spi
Introduction
Command descriptions of command
SPI
SPI
Api Basic Operation Principle
General Operation
The SPI
command set allows to operate the Serial Peripheral Interface SPI interface of the HadCon(2)'s microcontroller, (currently "only") as a master.
It sends data in atomic chunks of bytes via the MOSI
pin to slave devices and receives via the MISO
pin the responses.
This happens in a buffered mode, so that multiple bytes can be send and received at once.
The current limitation of the write-buffer is linked to the input string buffer of 140 characters, i.e. ≈ 60 bytes.
Up to 8 Chip-Select/SlaveS Select output pin(s) can be defined and manipulated either
The received data is stored in a read buffer which is of the same size as the write buffer.
The purging of the buffers depend on the mode of operation and the configuration settings.
Advanced Operation
The user can prepare step by step the write buffer before automatically sending it.
Example sequence: add/write_buffer
SPI purge_read_buffer // optionally
SPI purge_write_buffer // optionally
SPI add dc 7f
SPI add 8f8fb4 // repeat until write buffer is full
SPI add 0123456789abcdef //
SPI add be //
SPI show_write_buffer // optionally
SPI write_buffer
SPI write_buffer // e.g. repeat it, if auto_purge is OFF
SPI write_buffer 02 // only activate second chip select pin, by masking it with 0x02
The
write_buffer
command includes all remaining necessary steps:
- set cs
- setting the defined chip-select pin(s) to "active low"
- optionally masked by an external mask
- transmit/receive
byte by byte in the given byte-order
- transmit write buffer content
- attaching received bytes to the end of the read buffer
- release cs
- release the defined chip-select pins(s) to "passive high"
- optionally masked by an external mask
- optionally purge write buffer
Example sequence:
write/write_buffer
SPI write dc 7f 8f8fb4 0123456789abcdef be
SPI write_buffer // e.g. repeat it, if auto_purge is OFF
...
SPI write_buffer
SPI write_buffer 02 // only activate 2nd chip select pin, by masking it with 0x02
SPI write_buffer 01 // only activate 1st chip select pin
SPI write_buffer fc // only activate the other chip select pins
Reading: see
Basic Operation
Expert Operation
The user has full control on setting and releasing chip select pins.
Example sequence: selected chip select
SPI purge_read_buffer // optionally
SPI purge_write_buffer // optionally
SPI add dc 7f 8f8fb4 0123456789abcdef be
SPI cs // get status of defined chip select pins
SPI cs_bar // same as above but with "active low" logic
SPI cs_set // set all available chip select pins to "active"
SPI transmit
SPI cs_release // set all available chip select pins to "passive"
SPI cs_set 01 // only activate 1st chip select pin to "active"
SPI transmit
SPI cs_release // set all available chip select pins to "passive"
SPI cs_set fe // only activate the other chip select pins to "active"
SPI transmit
SPI cs_release ee // set masked chip select pins to "passive", keep 5th "active"
SPI cs_release 10 // set masked chip select pins to "passive", keep 5th "active"
Reading: see
Basic Operation
Main Commands
SPI
- Format
-
- Format
-
-
SPI <list of data bytes|words|dwords|qwords>
SPI w/write
- Task
- send list of bytes to clients, including predefined purge, chip-select behavior
- Format
-
-
SPI write <list of data bytes|words|dwords|qwords>
-
SPI w <list of data bytes|words|dwords|qwords>
- Response
-
- nothing
- if
DEBG
> 0 RECV SPI write OK
- Description
-
As described in section Basic Operation
- Arguments
-
- list of data bytes|words|dwords|qwords|...
- Comments
-
SPI a/add
- Task
- add list of data byte by byte to the write buffer
- Format
-
-
SPI add <list of data bytes|words|dwords|qwords>
-
SPI a <list of data bytes|words|dwords|qwords>
- Response
-
- nothing
- if
DEBG
> 0 RECV SPI add OK
- Arguments
-
- list of data bytes|words|dwords|qwords|...
- Comments
-
- Maximum single number length 24 digits
SPI wb/write_buffer
- Task
- send write buffer content to clients, including predefined purge, chip-select behavior,
optionally selecting chip select pins
- Format
-
-
SPI write_buffer [ <Chip Select Mask> ]
-
SPI wb [ <Chip Select Mask> ]
- Response
-
RECV SPI write_buffer
- Description
-
- Arguments
-
- optional: external chip select mask:
- [ 0 ... FF]
- each bit represents a cs pin
- Comments
-
SPI t/transmit
- Task
- send write buffer content to clients, w/o any chip select manipulation
- Format
-
- Response
-
- nothing
- if
DEBG
> 0 RECV SPI transmit OK
- Description
-
- Arguments
-
- Comments
-
SPI css/cs_set
- Task
- sets (selected) chip select pins to "active low"
- Format
-
-
SPI cs_set [ <Chip Select Mask> ]
-
SPI css [ <Chip Select Mask> ]
- Response
-
RECV SPI cs 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
- Description
- On success
cs
is called to show the current status
- Arguments
-
- optional: external chip select mask:
- [ 0 ... FF]
- each bit represents a cs pin
- Comments
-
SPI csr/cs_release
- Task
- releases (selected) chip select pins to "passive high"
- Format
-
-
SPI cs_release [ <Chip Select Mask> ]
-
SPI csr [ <Chip Select Mask> ]
- Response
-
RECV SPI cs 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
- Description
-
- Arguments
-
- optional: external chip select mask:
- [ 0 ... FF]
- each bit represents a cs pin
- Comments
-
SPI r/read
- Task
- read the last element filled into the read buffer
- Format
-
- Response
-
RECV SPI read <value>
- Description
- read the last element filled into the read buffer
depending on the transmit_byte_order : * 0, MSB: last element (FIFO) * 1, LSB: first element (LIFO)
- Arguments
-
- Return values
-
-
<value>
- "--" , if read buffer is empty
- last byte filled [0 .. FF]
- Comments
-
SPI sw/show_write_buffer
- Task
- show (partial) content of write buffer
- Format
-
-
SPI show_write_buffer [<Number of Bytes> [<Reverse Flag>]]
-
SPI sw [<Number of Bytes> [<Reverse Flag>]]
- Response
-
- w/o any arguments,
buffer filled, ≤ 8 bytes:
SPI sw
RECV SPI show_write_buffer elements: 0x5 (5)
RECV SPI show_write_buffer 10 00 10 21 42
- w/o any arguments,
buffer filled, > 8 bytes:
SPI sw
RECV SPI show_write_buffer elements: 0x14 (20)
RECV SPI show_write_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_write_buffer (#2) 10 10 10 00 10 21 42 51 ...
RECV SPI show_write_buffer (#3) 25 01 10 10
- w/
<Number of Bytes>
set, <Number of Bytes>
≠0,
buffer empty:
SPI sw 3
RECV SPI show_write_buffer --
- w/
<Number of Bytes>
set, e.g. 4,
buffer filled, ≤ 8 bytes:
SPI sw 4
RECV SPI show_write_buffer 10 00 10 21
- w/
<Number of Bytes>
set, e.g. 0xA,
buffer filled, > 8 bytes:
SPI sw a
RECV SPI show_write_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_write_buffer (#2) 10 10
- w/
<Number of Bytes>
set, e.g. 2,
w/ <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
)
buffer filled, ≤ 8 bytes,
SPI sw 2 TRUE
RECV SPI show_write_buffer 10 10
- w/
<Number of Bytes>
set, e.g. 9,
w/ <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
)
buffer filled, > 8 bytes:
SPI sw 9 1
RECV SPI show_write_buffer (#1) 00 10 21 42 51 25 01 10 ...
RECV SPI show_write_buffer (#2) 10
- Description
- Shows (partial) content of write buffer. Depending on the optional arguments the set can be reduced to a sub set of the buffer, beginning from the first element filled or reverse beginning with the last elements added. Depending on the number of elements requested, additional information is added:
- if all elements are show a summary line is added, with the given number of elements in the buffer in hex and decimal
- if the number of elements to show exceed
8
- a line counter
(#i)
, starting from 1, is added in front
- "..." are added at the end of the line, if more lines follow
- Arguments
-
-
<Number of Bytes>
- max number of bytes to show, ≥ 0
-
0
: all available
- else: show
<Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
-
<Reverse Flag>
- flag to revert direction of interest
-
0,FALSE,OFF,LOW
: show <Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
- else: show
<Number of Bytes>
elements from <number of elements> - <Number of Bytes>
until last added element
- Comments
-
SPI sr/show_read_buffer
- Task
- show (partial) content of read buffer
- Format
-
-
SPI show_read_buffer [<Number of Bytes> [<Reverse Flag>]]
-
SPI sr [<Number of Bytes> [<Reverse Flag>]]
- Response
-
- w/o any arguments,
buffer filled, ≤ 8 bytes:
SPI sr
RECV SPI show_read_buffer elements: 0x5 (5)
RECV SPI show_read_buffer 10 00 10 21 42
- w/o any arguments,
buffer filled, > 8 bytes:
SPI sr
RECV SPI show_read_buffer elements: 0x14 (20)
RECV SPI show_read_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_read_buffer (#2) 10 10 10 00 10 21 42 51 ...
RECV SPI show_read_buffer (#3) 25 01 10 10
- w/
<Number of Bytes>
set, <Number of Bytes>
≠0,
buffer empty:
SPI sr 3
RECV SPI show_read_buffer --
- w/
<Number of Bytes>
set, e.g. 4,
buffer filled, ≤ 8 bytes:
SPI sr 4
RECV SPI show_read_buffer 10 00 10 21
- w/
<Number of Bytes>
set, e.g. 0xA,
buffer filled, > 8 bytes:
SPI sr a
RECV SPI show_read_buffer (#1) 10 00 10 21 42 51 25 01 ...
RECV SPI show_read_buffer (#2) 10 10
- w/
<Number of Bytes>
set, e.g. 2,
w/ <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
)
buffer filled, ≤ 8 bytes,
SPI sr 2 TRUE
RECV SPI show_read_buffer 10 10
- w/
<Number of Bytes>
set, e.g. 9,
w/ <Reverse Flag>
flag set ( TRUE,HIGH,ON,1
)
buffer filled, > 8 bytes:
SPI sr 9 1
RECV SPI show_read_buffer (#1) 00 10 21 42 51 25 01 10 ...
RECV SPI show_read_buffer (#2) 10
- Description
- Shows (partial) content of read buffer. Depending on the optional arguments the set can be reduced to a sub set of the buffer, beginning from the first element filled or reverse beginning with the last elements added. Depending on the number of elements requested, additional information is added:
- if all elements are show a summary line is added, with the given number of elements in the buffer in hex and decimal
- if the number of elements to show exceed
8
- a line counter
(#i)
, starting from 1, is added in front
- "..." are added at the end of the line, if more lines follow
- Arguments
-
-
<Number of Bytes>
- max number of bytes to show, ≥ 0
-
0
: all available
- else: show
<Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
-
<Reverse Flag>
- flag to revert direction of interest
-
0,FALSE,OFF,LOW
: show <Number of Bytes>
elements from beginning (1) to maximum <Number of Bytes>
- else: show
<Number of Bytes>
elements from <number of elements> - <Number of Bytes>
until last added element
- Comments
-
Clean-up
SPI p/purge
- Task
- purge write and read buffer
- Format
-
- Response
-
- nothing
- if
DEBG
> 0 RECV SPI purge OK
- Description
- purges write and read buffer, by internally calling
purge_write_buffer
and purge_read_buffer
- Arguments
-
- Comments
-
SPI pw/purge_write_buffer
- Task
- purge write buffer
- Format
-
-
SPI purge_write_buffer
-
SPI pw
- Response
-
- Description
-
- Arguments
-
- Comments
-
- only resets the number of elements to 0, not the data
SPI pr/purge_read_buffer
- Task
- purge read buffer
- Format
-
-
SPI purge_read_buffer
-
SPI pr
- Response
-
- Description
-
- Arguments
-
- Comments
-
- only resets the number of elements to 0, not the data
SPI reset
- Task
- resets SPI interface and SPI parameter settings to their default status
- Format
-
- Response
-
- nothing
- if
DEBG
> 0 RECV SPI reset OK
- Description
-
- Arguments
-
- Comments
-
Status
SPI s/status
- Task
- Show status
- Format
-
- Response
-
RECV SPI status
RECV SPI cs 1:0 2:- 3:- 4:- 5:- 6:- 7:- 8:-
RECV SPI cs_bar 1:1 2:- 3:- 4:- 5:- 6:- 7:- 8:-
RECV SPI cs_pins 1:PORTB,0
RECV SPI cs_select_mask FF
RECV SPI control_bits 50
RECV SPI spi_enable TRUE
RECV SPI data_order 0
RECV SPI master TRUE
RECV SPI clock_polarity 0
RECV SPI clock_phase 0
RECV SPI speed 0
RECV SPI double_speed TRUE
RECV SPI speed_divider 4 (2500000Hz @ 10000000Hz)
RECV SPI transmit_byte_order 0 (MSB/big endian)
RECV SPI transmit_report FALSE
RECV SPI auto_purge_read_buffer TRUE
RECV SPI auto_purge_write_buffer FALSE
RECV SPI show_write_buffer elements: 0xd (13)
RECV SPI show_write_buffer (#1) AB BB AA BB CC EE FF 66 ...
RECV SPI show_write_buffer (#2) 54 12 45 54 58
RECV SPI show_read_buffer elements: 0 (0)
- Description
-
- recursive call of all available status information
- Arguments
-
- Comments
-
SPI cs
- Task
- reports current status of (selected) chip select lines
- Format
-
-
SPI cs [<Chip Select Mask>]
- Response
-
- Description
-
- Arguments
-
- optional
[<Chip Select Mask>]
- [ 0 ... FF]
- each bit represents a cs pin
- Response
-
- list of
<Pin States>
- syntax
<Pin States>
:
-
<Index>:<State>
-
<Index>
: 1 ... 8
-
<State>
:
-
1
: HIGH
-
0
: LOW
-
-
: undefined, channel not connected
- Comments
-
SPI csb/cs_bar
- Task
- reports current inverted status of (selected) chip select lines
- Format
-
-
SPI cs_bar [<Chip Select Mask>]
-
SPI csb [<Chip Select Mask>]
- Response
-
- Description
-
- Arguments
-
- optional
<Chip Select Mask>
- [ 0 ... FF]
- each bit represents a cs channel/pin
- Response
-
- list of
<Pin States>
- syntax
<Pin States>
:
-
<Index>:<State>
-
<Index>
: 1 ... 8
-
<State>
:
-
1
: LOW
-
0
: HIGH
-
-
: undefined, channel not connected
SPI cs_pins
- Task
- report current chip select channel configurations
- Format
-
-
SPI cs_pins [<CS Channel Index>]
- Response
-
- w/o argument
SPI cs_pins
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
- e.g.:
RECV SPI cs_pins 1:PORTB,0 2:PORTA,4 3:PORTG,4 7:PORTF,5
- w/
<CS Channel Index>
SPI cs_pins <CS Channel Index>
RECV SPI cs_pins <Index><PORTx>,<Pin>,<Status>
- Description
-
- Arguments
-
- optional
<CS Channel Index>
- chip select index
-
1 ... 8
- Return values
-
-
<List of active <Index>:<PORTx>,<Pin> CS Configurations>
or
<<Index>:<PORTx>,<Pin>,<Status> CS Configuration>
-
<Index>
- chip select index
-
1 ... 8
-
<PORTx>
-
<Pin>
-
<Status>
- status of chosen chip select index
-
ON
: active
-
OFF
: deactivated
- Comments
-
Chip Select Configuration
SPI cs_select_mask
- Task
- get / set external chip select mask
- Format
-
-
SPI cs_select_mask [<Chip Select Mask>]
- Response
-
RECV SPI cs_select_mask <Value>
- Description
- The chip select mask allows to select a subset of the available, defined chip select channels.
Each bit of this mask represents a channel which can be selected or ignored.
This mask is used in all cases where chip select actions are required and not explicitly given.
- w/o argument: the current mask is shown
- w/ argument:
<Value>
is assigned to the configuration
- Arguments
-
- optional,
<Value>
- chip select mask
- range
[0 ... FF]
- each bit represents a chip select channel
- Comments
-
SPI csap/cs_add_pin
- Task
- add chip select channel configuration
- Format
-
-
SPI cs_add_pin <Symbolic Output Port Address> <Output Port Pin> [<Channel Select Index/Slot>]
-
SPI csap <Symbolic Output Port Address> <Output Port Pin> [<Channel Select Index/Slot>]
- Response
-
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
see SPI cs_pins
- Description
- Allows to add up to 8 output port
PORTX:Pin
combinations to act as channel select channels. Provided the chosen slots aren't used yet or the address set is already defined (see SPI cs_pins, SPI cs_remove_pin).
A successful operation is reported via SPI cs_pins
- w/o
<Channel Select Index/Slot>
:
- adds channel to next free slot
- w/
<Channel Select Index/Slot>
:
- adds channel to assigned index
- Arguments
-
-
<Symbolic Output Port Address>
- symbolic name for the available output port addresses
-
<Output Port Pin>
- optionally
<Channel Select Index/Slot>
- Comments
-
SPI csrp/cs_remove_pin
- Task
- remove chip select channel configuration
- Format
-
-
SPI cs_remove_pin <Channel Select Index/Slot>
-
SPI csrp <Channel Select Index/Slot>
- Response
-
RECV SPI cs_pins <List of active <Index>:<PORTx>,<Pin> CS Configurations>
see SPI cs_pins
- Description
- Removes a chip select configuration from set of pin configuration (see SPI cs_pins).
A successful operation is reported via SPI cs_pins.
- Arguments
-
-
<Channel Select Index/Slot>
- Comments
-
SPI Configuration
SPI c/control_bits
- Task
- set/get SPI hardware configuraton/status
- Format
-
-
SPI control_bits [<Extended SPI Control Register>]
-
SPI c [<Extended SPI Control Register>]
- Response
- e.g. :
RECV SPI control_bits 50
RECV SPI spi_enable TRUE
RECV SPI data_order 0
RECV SPI master TRUE
RECV SPI clock_polarity 0
RECV SPI clock_phase 0
RECV SPI speed 0
RECV SPI double_speed TRUE
RECV SPI speed_divider 4 (2500000Hz @ 10000000Hz)
- Description
- Allows to set/get the combined information/settings of the SPI Control Register
SPCR
and the SPI Status Register SPSR
en bloc. Therefore those two registers are combinded into one 16bit data word with SPCR
as LSB and SPSR
as MSB. Since SPSR
, despite its name, does have one control bit.
- w/o
<Extended SPI Control Register>
:
- w/
<Extended SPI Control Register>
:
- Note
- all settings can be done alone using the functions described below. Success is reported via its get mode and the get functions of the seperate properties.
- Arguments
-
-
<Extended SPI Control Register>
- Comments
-
SPI spi_enable
- Task
- get/set spi configuration's bit
SPI enable state: SPE
- Format
-
- Response
-
RECV SPI spi_enable ==SPI enable state: SPE==
- Description
- "When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operation."
(from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI data_order
- Task
- get/set spi configuration's bit
SPI Data Order: DORD
- Format
-
- Response
-
RECV SPI data_order
- Description
- "When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. "
(from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI master
- Task
- get/set spi configuration's bit
SPI Master/Slave Select: MSTR
- Format
-
- Response
-
RECV SPI master
- Description
- "This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS [the 'Chip Select Pin'] is configured as an input and is driven low while MSTR is set, MSTR will be cleared"
(from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
(0,) 1, ≠0, ON, (OFF), TRUE, (FALSE)
- Comments
-
- Slave mode not implemented
SPI clock_polarity
- Task
- get/set spi configuration's bit
SPI Clock Polarity: CPOL
- Format
-
-
SPI clock_polarity [<value>]
- Response
-
RECV SPI clock_polarity
- Description
- "When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle."
(from Manual: AT90CANxx)
-
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI clock_phase
- Task
- get/set spi configuration's bit
SPI Clock Phase: CPHA
- Format
-
-
SPI clock_phase [<value>]
- Response
-
RECV SPI clock_phase
- Description
- "The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK." (from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI speed
- Task
- get/set spi configuration's bits
SPI Clock Rate Select 1/0: SPR1/0
- Format
-
- Response
-
RECV SPI speed
- Description
- "These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. "
(from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
- Comments
-
SPI speed_divider
- Task
- get/set spi configuration's
Clock Rate Divider
- Format
-
-
SPI speed_divider [<value>]
- Response
-
RECV SPI speed_divider
- Description
- Set the ratio between fclkIO and
SCK frequency
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
2, 4, 8, 0x10, 0x20, 0x40, 0x80
- Comments
-
SPI double_speed
- Task
- get/set spi configuration's bit
SPI Double Speed Bit: SPI2X
- Format
-
-
SPI double_speed [<value>]
- Response
-
RECV SPI double_speed
- Description
- "When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode. This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fclkio/4 or lower."
(from Manual: AT90CANxx)
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
API Configuration
SPI transmit_byte_order
- Task
- get/set the transmit order the data bytes of the buffer are written to the devices
- Format
-
-
SPI transmit_byte_order [<value>]
- Response
-
RECV SPI transmit_byte_order
- Description
-
- w/o argument: get value
- w/ argument: set value
- Arguments
-
- Comments
-
SPI transmit_report
- Task
- get status of / enable/disable additional transmission reports after sending the write buffer
- Format
-
-
SPI transmit_report [<value>]
- Response
-
RECV SPI transmit_report
$ Description:
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI auto_purge_write_buffer
- Task
- get status of / enable/disable automatic write buffer purge after sending its content
- Format
-
-
SPI auto_purge_write_buffer [<value>]
- Response
-
RECV SPI auto_purge_write_buffer
$ Description:
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
SPI auto_purge_read_buffer
- Task
- get status of / enable/disable automatic read buffer purge before sending data
- Format
-
-
SPI auto_purge_read_buffer [<value>]
- Response
-
RECV SPI auto_purge_read_buffer
$ Description:
- w/o argument: get value
- w/ argument: set value
- Arguments
-
-
<value>
-
0, 1, ≠0, ON, OFF, TRUE, FALSE
- Comments
-
--
PeterZumbruch - 13 Jan 2014